Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.

Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. The received analog signal is evaluated using a detection portion of the analog section to determine when background noise on the analog signal is exceeded. A feature extraction portion of the analog section is triggered to extract sparse sound parameter information from the analog signal when the background noise is exceeded. An initial truncated portion of the sound parameter information is compared to a truncated sound parameter database stored locally with the sound recognition sensor to detect when there is a likelihood that the expected sound is being received in the analog signal. A trigger signal is generated to trigger classification logic when the likelihood that the expected sound is being received exceeds a threshold value.

Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sound parameter information is extracted from the analog signal and compared to a sound parameter reference stored locally with the sound recognition sensor to detect when the signature sound is received in the analog signal. A trigger signal is generated when a signature sound is detected. A portion of the extracted sound parameter information is sent to a remote training location for adaptive training when a signature sound detection error occurs. An updated sound parameter reference from the remote training location is received in response to the adaptive training.

Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.

Abstract: A network of sensor and controller nodes having the ability to be dynamically programmed and receive updated software from one another, and from a host system. Each network node includes multiple state machines, at least some of which are operable relative to physical pins at the network node; the physical pins correspond to inputs from sensor functions or outputs to control functions. The network nodes include microcontrollers that are operable in an operating mode to execute a state machine and respond to commands from other nodes or the host, and in a read mode to receive and store program instructions transmitted from other nodes or the host. A learn mode is also provided, by way of which a network node can store program code corresponding to instructions and actions at the node when under user control.

Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

Abstract: A camera points in a first direction and is positioned within borders of a screen of a display device. The screen faces in a second direction that is substantially parallel to the first direction. While the camera views a scene, the screen displays an image of the viewed scene. While the screen displays the image, the image is written for storage on a computer-readable medium.

Abstract: A method of making an electrical assembly includes making a laminate substrate, embedding a plurality of integrated circuit dies in the laminate substrate, forming a plurality of through-holes in the laminate substrate and adding conductive material to the through-holes, and making at least one saw cut extending through the laminate substrate and through the plurality of through-holes and the conductive material therein to form at least one laminate block with a cut face and a plurality of sectioned through-holes.

Abstract: Apparatus and methods are described for creating multiple different heads-up display (HUD) images at different apparent distances from a viewer using a single picture generator. First and second images are generated using respective first and second subsets of modulating elements of an array of image pixel modulating elements of a spatial light modulator. Light from the first and second images is directed along respective first and second optical paths onto a transparent display surface to form respective first and second virtual images at different apparent distances within a field of view of a viewer looking through the display surface. In a described example, the modulating elements are micromirrors of a digital micromirror device (DMD) and optical elements of the respective optical paths are relatively movable to set relative path lengths.

Abstract: From at least a first microphone, first microphone signals are received that represent first sound waves. From at least a second microphone, second microphone signals are received that represent second sound waves. In response to the first microphone signals, first noise in the first sound waves is estimated, and first cancellation signals are output for causing a speaker array to generate first additional sound waves via at least a first acoustic beam for cancelling at least some of the first noise. In response to the second microphone signals, second noise in the second sound waves is estimated, and second cancellation signals are output for causing the speaker array to generate second additional sound waves via at least a second acoustic beam for cancelling at least some of the second noise.

Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is extracted from the analog signal. The extracted sparse sound parameter information is processed using a sound signature database stored in the sound recognition sensor to identify sounds or speech contained in the analog signal, wherein the sound signature database comprises a plurality of sound signatures each representing an entire word or multiword phrase.

Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is extracted from the analog signal and compared to a sound parameter reference stored locally with the sound recognition sensor to detect when the signature sound is received in the analog signal. A portion of the sparse sound parameter information is differential zero crossing (ZC) counts. Differential ZC rate may be determined by measuring a number of times the analog signal crosses a threshold value during each of a sequence of time frames to form a sequence of ZC counts and taking a difference between selected pairs of ZC counts to form a sequence of differential ZC counts.

Abstract: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

Abstract: A method of operating a power factor correction (PFC) circuit and a corresponding power factor correction circuit include determining an adaptive switching frequency of the PFC circuit related to a current of the boost inductor of the PFC circuit, and operating the PFC circuit at a light load based on the adaptive switching frequency.

Abstract: In accordance with the teachings of the present disclosure, a method and system for the timing color of an image display are provided. In one embodiment, a method for displaying image includes sequentially illuminating a spatial light modulator with a plurality of colors by shining light through a color wheel having a plurality of adjacent color segments. The method further includes determining, a time period in which the output of the color wheel is deemed not to correspond solely to either of the two adjacent color segments for at least a portion of the spatial light modulator. The time period is based at least in part on the luminance difference between two adjacent color segments in the color wheel.

Abstract: The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of a switch mode DC-DC converter. The electronic device is configured to reduce a bias current of the comparator with a first slope in response to a decreasing load and to increase the bias current of the comparator with a second slope in response to an increasing load, wherein the second slope is steeper than the first slope.

Abstract: An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.