Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.

Abstract: A method of detecting uninitialized memory reads is shown where either all or a subset of a random access memory system is initialized to a know value. One or more watch points are implemented where after a memory read is detected the value read is compared to the value written during initialization. If the values match debug information is captured and appropriate corrective action is taken.

Abstract: A system configured for charging and distribution control is provided. The system includes a switching regulator, a control circuit and a first converter. The switching regulator is configured to be selectively operable in one of a first operative state and a second operative state based on a control signal. The first operative state and the second operative state are associated with a maximum level of an alternator output power corresponding to at least one alternator operational feature, at least one alternator operational feature being associated with the alternator output voltage and an alternator speed. The control circuit is configured to generate the control signal based at least on the at least one alternator operational feature. The first converter is configured to generate a first converter output voltage based on the regulated DC output voltage. The first converter output voltage is lower than the regulated DC output voltage.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space.

Abstract: A method of improving the perceptual video quality of video sequences containing black bars. Horizontal or vertical black bars caused by a missmatch between the aspect ratio of the encoded video and the display device. The presence of black bars is detected, and the encoding process is adjusted to eliminate visual depredation of the reproduced video.

Abstract: At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to obtain values indicative of a state of an operating context parameter during execution of a traced program on a target processor, and display an indication of a proportion of time during a trace period of the traced program that the target processor operated with the operating context parameter in a particular state.

Abstract: Methods and systems for amplitude modulation in a parametric speaker system are provided that perform truncated double sideband (TDSB) frequency modulation of audio signal in which most of the processing is performed in the frequency domain, thus permitting use of fast processing techniques for amplitude modulation (AM) and filtering and reducing computation cost over time domain processing. A maximum envelope value of the time domain audio signal may be to the carrier signal in the frequency domain that avoids emitting the carrier signal when the input signal level is low or mute. The application of the envelope value may be smoothed to reduce discontinuity at input block boundaries.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based on the output signal, where the offset sensor includes a second amplifier configured to generate an offset reduction signal for the first amplifier based on the sensed DC offset. A T-network in the circuit includes at least three resistors coupled to provide a feedback connection between the input signal and the output signal for the first amplifier and to receive the offset reduction signal to mitigate DC offset in the first amplifier. Since this method reduces the low-frequency component of the signal, it also shapes and reduces the flicker noise.

Abstract: A system for correcting gain imbalance and phase imbalance between first (IOUT) and second (QOUT) signals which are 90° out of phase, including circuitry for estimating the phase mismatch (?) and gain mismatch (?) between the first signal and the second signal signals in a plurality of frequency bands. An inverse fast Fourier transform is performed on each of a number of arrays of the phase mismatch estimates and the gain mismatch estimates to generate correction filter coefficients (h[N]) for a N tap correction filter. The N tap correction filter filters an uncorrected value of the second signal to generate a corrected value of the second signal.

Abstract: A method and apparatus for motion estimation utilizing adaptive sliding window algorithm, the method includes estimating motion estimation search window size, transferring data from a previous picture relating to the search window, wherein the size of the search window is determined, and calculating motion vector of the current block by block matching the current block with data of the previous picture in search window.

Abstract: A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.