Abstract: An apparatus for controlling a power converter operating in response to a modulating signal during successive switching cycles includes: (a) A signal sensor coupled with the converter and sensing an extant signal during the extant cycle. (b) A signal level predictor coupled for receiving a reference signal and establishing a predicted level for the extant switching cycle. (c) A comparer coupled with the signal sensor and the signal level predictor for presenting a first output signal when the extant signal and the predicted signal level have a first relationship and for presenting a second output signal when the extant signal and the predicted signal level have a second relationship. (d) A control unit coupled with the comparer and with the converter for interrupting presentation of the modulating signal to the converter device when the comparing unit presents a selected one of the first and second output signals.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and operable to combine the first and second signals to create a third signal, one or more down converters operable to receive respective output signals from respective electronic devices and create respective down converted signals, and a set of switches operable to switch the second RF source to a local oscillator function that couples to the one or more down converters for inputting respective reference signals into the one or more down converters.

Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Abstract: A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The system also includes a system memory coupled to the processor, wherein the system memory stores RAM resize instructions that, when executed, enable the public RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions that, when executed, enable a cryptographic hardware accelerator (HWA) to be shared by a secure application and a public application.

Abstract: The present invention provides a lubricant container inside a microelectromechanical device package. The lubricant container contains selected lubricant that evaporates from the container and contact to a surface of the microelectromechanical device for lubricating the surface.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: Disclosed is a system for adjusting a plurality of component color signals for expanded color gamut displays. The disclosed system comprises an input for receiving the component color signals, a detection circuit (502) connected to the input and configured to detect at least one characteristics of the received component color signals, and an adjustment circuit (504) connected to the input for receiving the component color signal and for creating adjusted component color signals from the received component color signals according to a certain technique, where the certain technique is changed according to the detected characteristic.

Abstract: Described embodiments provide for an optical communications assembly or other optical assembly in which the post-dispersion optical signals are controlled in dispersive and non-dispersive directions. In one embodiment, the assembly includes an optical signal collimator configured to emit an optical signal based on an input communication signal. In addition, the assembly includes a dispersive device that receives the optical signal and disperses multiple wavelength channels of the optical signal in a dispersive direction. The assembly further includes a first light-directing device configured to control the dispersion of the multiple wavelength channels in the non-dispersive direction. A second light-directing device is provided to control dispersion in the dispersive direction.

Abstract: A CDMA receiver (500) minimizes the use of hardware by taking advantage of the fact that Walsh sequences of a predetermined length (e.g., 16) are comprised of inverted and non-inverted versions of smaller length (e.g., 4) sequences. The receiver (500) performs the necessary uncovering operations for example of a Walsh sequence of length 16 by performing uncovering operations using smaller length Walsh sequences such as of length 4 and then performing subsequent summing operations with inverted and non-inverted versions of the results of such uncovering operations.

Abstract: A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of the interface layer 140 and performing a second low temperature anneal to complete the formation of a low resistance silicide 160.

Abstract: Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to measure the power consumption of an embedded application at the task level as the application is executing on the target hardware. Methods and apparatus are provided to permit such measurements in both real-time and non-real-time.

Abstract: According to one embodiment, a method of increasing a perceived resolution of a display includes directing light at a optical dithering element and repeatedly transitioning the optical dithering element from a first position to a second position and then back to the first position such that the mirror alternately reflects light to a first position on the display and then to a second position on the display. Each transition of the mirror includes controlling any overshoot or ringing in the position of the optical dithering element by providing a predetermined drive signal to the optical dithering element to smoothly accelerate and decelerate the element during the traverse between the first and second positions.

Abstract: A system operable for ranging synchronization is provided. The system includes a first component that is operable to analyze a set of signals. The first component is operable to determine a subset of the set of signals based on a condition, at least some of the set of signals including ranging codes. The system also includes a second component that is operable to receive the subset of the set of signals and to determine a preferred candidate of ranging codes.

Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.

Abstract: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer through orifices (110) contained in the spokes (90).

Abstract: A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in order to gain a full understanding of how code is being executed by the processor.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.