Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: Embodiments provide a method to accommodate clock drift and guard time in a distributed fashion. A first device is adapted to communicate with a second device. A clock in the first device is synchronized to a clock in the second device using beacon or/and acknowledgement frames from the second device. A nominal guard time is computed that accounts for clock drift in the first and second devices during a nominal synchronization interval. An additional guard time is computed that accounts for clock drift in the first and second devices during an additional interval beyond the nominal synchronization interval. An available transmission interval is determined within an allocation interval for transmissions between the devices, wherein the beginning and/or the end of the available transmission interval are selected by accounting for the nominal guard time and/or the additional guard time. One or more frames are transmitted within the available transmission interval.

Abstract: A system and method for establishing a pairwise temporal key (PTK) between two devices based on a shared master key and using a single message authentication codes (MAC) algorithm is disclosed. The devices use the shared master key to independently compute four MACs representing the desired PTK, a KCK, and a first and a second KMAC. The Responder sends its first KMAC to the Initiator, which retains the computed PTK only if it verifies that the received first KMAC equals its computed first KMAC and hence that the Responder indeed possesses the purportedly shared master key. The Initiator sends a third message including the second KMAC to the Responder. The Responder retains the computed PTK only if it has verified that the received second KMAC equals its computed second KMAC and hence that the Initiator indeed possesses the purportedly shared master key.

Abstract: A method of powerline communications including a first node and at least a second node on a powerline communications (PLC) channel in a PLC network. The first node sends a physical layer (PHY) data frame on the PLC channel including a preamble, a PHY header, a MAC header and a MAC payload. The MAC header includes a Cyclic Redundancy Check (CRC) field (MH-CRC field). The second node receives the data frame, parses the MAC header to reach the MH-CRC field, and performs CRC verification using the MH-CRC field to verify the MAC header. If the CRC verification is successful, (i) the second node parses another portion of the MAC header to identify a destination address of the data frame and (ii) to determine whether the data frame is intended for the second node from the destination address.

Abstract: One embodiment relates to power conversion system. The system includes a converter configured to convert an input voltage to an output voltage, the converter comprising at least one switch that is controlled in response to an activation signal to provide current through an inductor. A transition mode controller is configured to provide the activation signal based on a measure of charge derived from current through the switch and based on the current through the inductor.

Abstract: Embodiments support stringent Quality of Service (QoS) requirements using adaptations to the existing Bluetooth Low Energy (BLE) protocols. In systems using an enhanced BLE protocol, the master send a poll frame at selected connection intervals or poll intervals. The duration of the connection interval and/or poll interval may be calculated based upon desired QoS parameters, such as delay, target packet error rate (PER), frame error rate (FER), and/or jitter. The master may consider the connection interval lost if a frame is not received from the slave after a predetermined number (m) of consecutive poll frames are transmitted. The value m may be set relatively high to provide more robustness in the system. However, the poll interval may also need to be adjusted to meet QoS requirements. The slave may be required to transmit a packet—that may or may not carry data—in response to every mth received poll.

Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.

Abstract: An aspect of the present invention includes a circuit having a cascaded H-bridge, an upper voltage supply component, a lower voltage supply component and a pre-driver component. The cascoded H-bridge is arranged to provide a driving signal for driving a load. The upper voltage supply component can provide an upper supply voltage to the cascoded H-bridge. The lower voltage supply component can provide a lower supply voltage to the cascaded H-bridge. The pre-driver component can provide a pre-driving signal to the cascoded H-bridge, wherein pre-driver component has a first voltage source and a second voltage source. The first voltage source can provide an upper swing voltage and the second voltage source can provide a lower swing voltage. The pre-driver component can provide the pre-driving signal based on the upper swing voltage, the lower swing voltage and one of the upper supply voltage and the lower supply voltage.

Abstract: Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation coil using a bridge circuit connected to the excitation coil and having lower transistors for switched selective connection to a current mirror input transistor to mirror a current provided by pulsed current source, and with integrated filtering to control pulse rise times and slew rate.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: Compact, low power fluxgate magnetic sensor readout circuits and apparatus are presented in which demodulator or rectifier circuit to modulates a sense signal from the fluxgate sense coil, and the demodulated signal is provided to an amplifier circuit with a transconductance or other amplifier and one or more feedback capacitors connected between the amplifier input and amplifier output to integrate the amplifier output current and provide a voltage output signal indicating the magnetic field sensed by the fluxgate sensor.

Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract: Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method may include transmitting a one-hop broadcast request message to a plurality of PLC devices in a mesh network and receiving a response from each of the devices. The method may also include selecting one of the devices as a bootstrapping agent, sending a join request to a bootstrapping server through the bootstrapping agent, and, in response to successfully joining the network, setting the bootstrapping agent as a next hop toward a bootstrapping server. In another embodiment, a method may include maintaining a routing table for a plurality of PLC devices in a mesh network, receiving a join request from a PLC device, accepting the request, and updating the table to add a record corresponding to the PLC device; the record setting the bootstrapping agent as a penultimate hop toward the PLC device.

Abstract: A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.

Abstract: A window is displayed on a display device. The window includes at least first and second portions thereof. In response to a user selecting the first portion of the window on the display device, a first set of keys are displayed on the display device. The first set of keys are operable by the user to specify a first type of information within the first portion of the window. In response to the user selecting the second portion of the window on the display device, a second set of keys are displayed on the display device. The second set of keys are operable by the user to specify a second type of information within the second portion of the window. The second type of information includes at least some information that is unsupported by operation of the first set of keys.

Abstract: A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (TSVs), while the chips are free of TSVs. The TSVs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110). Symmetrically positioned relative to interposer (120), and connected to it by short signal traces, chips (130, 140) are attached to the TSVs of interposer 110, which in turn is attached to a substrate (160) with supply connections.

Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

Abstract: A method of powerline communications (PLC) includes compiling a data frame for physical layer (PHY) by a first communications device at a first communications node on a powerline of a PLC network. The data frame includes a single tone PHY header portion and a data payload portion in a set of tones including at least one tone having a frequency different from a frequency of the single tone. The PHY header portion includes tone mask identification information identifying the set of tones. The first communications device transmits the data frame over the powerline to a second communications device at a second communications node on the powerline. The second communications device receives the data frame, and decodes the data payload using the tone mask identification information in the PHY header portion.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal.