Abstract: A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The system also includes a system memory coupled to the processor, wherein the system memory stores RAM resize instructions that, when executed, enable the public RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions that, when executed, enable a cryptographic hardware accelerator (HWA) to be shared by a secure application and a public application.

Abstract: An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract: A voltage feedback loop employed with a power distribution switch rapidly responds to a predetermined drop in output voltage to increase the resistance of the switch for a predetermined time. After this predetermined time, a current feedback loop controls the resistance until the output voltage recovers, while also isolating the voltage feedback loop from the switch.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of the power FET, and its source coupled to an output node. A first feedback loop is coupled to the gate of the switching FET to facilitate sensing rising gate voltage. A second feedback loop is coupled to the gate of the switching FET to facilitate sensing falling gate voltage.

Abstract: Hybrid magnetic current sensors and sensing apparatus are presented with closed-loop and open-loop circuitry employs first and second integrated magnetic sensors to sense a magnetic field in a magnetic core structure gap to provide high accuracy current measurement via a closed-loop magnetic circuit with the first sensor in a nominal current range as well as open-loop current measurement using the second sensor in an extended second range to accommodate over-current conditions in a host system as well as to provide redundant current sensing functionality.

Abstract: A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and inserting a trace data gap into the trace data stream. The gap may contain additional information relating to the amount and type of data that is being lost during the overflow condition. In an alternate embodiment the generated trace may be throttled to ensure the available bandwidth is not exceeded.

Abstract: The present invention provides a system and method for combining asymmetrical camera views from a front racing and a back facing camera. Resizing and quality enhancement techniques are used to bring both front and back camera to same quality. Further, a panoramic mode of from camera and back camera are utilized to create a uniform stitching.

Abstract: Power over Ethernet (PoE) communication systems, control circuits and methods are presented for controlling power delivered to a powered device through a communication cable, in which a power sourcing equipment measures a supply voltage and selectively discontinues provision of power from a power source in response to a measured supply current exceeding an adaptive limit signal representing a supply current level corresponding to a predetermined safe operating power level at the measured supply voltage.

Abstract: Methods, electronic devices and USB charger apparatus are presented for fast USB charging, in which a high voltage master of the device detects a connected high voltage charger and selectively connects a current circuit to source or sink a current to or from one USB cable data signal conductor while providing a non-zero voltage to the other USB cable data signal conductor to configure the charger apparatus to provide charging power at a particular high voltage level above a nominal voltage level.

Abstract: In the present disclosure, an error in the velocity and position computed from a three dimensional IMU measurement is reduced confined by computing an auxiliary speed in a drive direction of a vehicle from an angular velocity measurement and a lateral acceleration measurement. The auxiliary speed is then compared with the speed computed from the acceleration measurement. The auxiliary speed is provided as the speed of the vehicle mounted with the IMU when the absolute difference between the auxiliary speed and the speed computed from the acceleration measurement in the drive direction is above a threshold. The auxiliary speed is computed when the vehicle is detected to be in a curved motion. According to another aspect of the present disclosure, the bias errors are determined when the vehicle is in a steady state, at rest or in a straight line motion. The bias errors are used to obtain the accurate auxiliary measurement.

Abstract: A method of manufacturing a thermometer probe includes: obtaining a hollow housing having an open end and a curved inner surface; obtaining a flexible detecting component having an adhesive layer; obtaining an insertion component; detachably attaching the flexible detecting component to the insertion component; inserting the insertion component, having the flexible detecting component attached thereto, through the open end of the hollow housing and into the hollow housing such that the adhesive layer is disposed between the insertion component and the inner surface; and adhering, via the adhesive layer, the flexible detecting component to the curved inner surface.

Abstract: A method of viewer attention controlled video playback on a video display device is provided that includes displaying a video on a display included in the video display device, determining whether or not attention of a viewer watching the video is focused on the display, and halting the displaying of the video when the attention of the viewer is not focused on the display.

Abstract: Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.

Abstract: A packaged semiconductor device has a semiconductor substrate with circuitry formed thereon. A shield plate is mounted over a designated region of the substrate and separated from the semiconductor substrate by a separator, such that the shield plate is separated from the designated region of the substrate by a distance. Mold compound encapsulates the semiconductor substrate and the shield plate, but is prevented from touching the designated region of the substrate by the shield plate.

Abstract: An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.

Abstract: A base station selects a subset of at least one geographically separated antennas for each of the plurality of user equipments. The base station forms at least layer of data stream including modulated symbols, precodes the data stream via multiplication with the NT-by-N precoding matrix where N is the number of said layers and NT is the number of transmit antenna elements and transmits the precoded layers of data stream to the user equipment via the selected geographically separated antennas. The base station signals the subset of the plurality of geographically separated antennas via higher layer Radio Resource Control or via a down link grant mechanism. The base station optionally does not signal the subset of the plurality of geographically separated antennas to the corresponding mobile user equipment.