Abstract: A three dimensional display system 100 using two spatial light modulators and a single projection path. Light source 102 emits a white light beam 104 which typically is focused onto an aperture of a recycling integrator 106. The light beam travels through the recycling integrator 106 and is reflected several times by the walls of the integrator 106. The sequential color filter creates a filtered light beam comprised of at least three spatially separated light beams. The filtered light beam, containing the colored filtered sub-beams, is separated by a polarizing beam splitter 116 into two separate light beams, each comprising a portion of each color sub-beam created by the sequential color filter. A first portion of the light beam having a first polarization state is passed to a first spatial light modulator 112. A second portion of the light beam having a second polarization state is reflected to a second spatial light modulator 114.

Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a selection system, such as a multiplexer, or a single load can be utilized. Feedback from the load is provided to the driver for achieving the desired operating level. A zero temperature coefficient resistance formed by two resistors having different resistances can be used so that the driver emulates an ideal resistor having a substantially zero temperature coefficient, providing a temperature independent current to the load.

Abstract: A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this first station has a first entrance (101a) and a first exit 101b). A second work station (102) is operable to perform a second manufacturing action on the product parts; this second station has a second entrance (102a) and a second exit (102b). A transport line (103) between the first exit and the second entrance is operable to move the product parts under computer control. A chamber (104) encloses a portion of the line and is constructed so that the transport achieves a balanced throughput from the first station to the second station, while the product parts are exposed to computer-controlled environmental conditions (110) during transport through the chamber. The balanced throughput in the chamber is achieved by waiting lines for the product with computer-controlled monitors (105a) for product parts' positions and times in the chamber.

Abstract: An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase generator receives a high speed clock, and generates P phases of the source clock to define P phase sectors. The phase selector selects respective pairs of phases such that each pair bounds a respective phase sector. The phase interpolator introduces at least one phase of the source clock between each pair of phases to provide Q phases of the source clock within each sector. The phase interpolator uses the phases of the source clock to produce lagging (leading) phase shifts of 360/P(Q?1) degrees, thereby generating the output clock having a stepped up or stepped down frequency.

Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element approximately between a plurality of desired positions by a generally periodic drive waveform. During a particular period of the drive waveform, the actual position of the optical dithering element is determined at a plurality of sample times. For each of the determined actual positions of the optical dithering element, a position error indicator is determined based upon whether the magnitude of the actual position is greater than, less than, or the same as a desired setpoint for the position of the optical dithering element. The method also includes generating an error signature for the particular period based on the determined error indicators and modifying the drive waveform in response to the error signature.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: A method for providing configuration information for use in installing a new wireless station to a wireless network that minimizes errors is presented. The configuration information is distributed by storing the configuration information onto a device with a memory and then distributing the device to the users interested in installing new wireless stations. The device is attached to a computer to which the wireless station is coupled, initiating a transfer of the configuration information. The computer uses the configuration information to configure the wireless station. The method also provides a way to limit access to the configuration information through the use of encryption and limiting the number of times the configuration information is retrieved. The method is also an effective way to distribute security keys for encryption systems whose purpose is to secure communications in a wireless network.

Abstract: A Hybrid IMMSE-LMMSE receiver processing technique predicts performance of and selects between iterative and non-iterative decoding of symbols based on an intelligent metric. Based on a pre-specified criterion, the receiver determines if a correct first-stage decision is made or not. If a correct decision is made, then it follows iterative processing like in BLAST. Alternatively, if a wrong decision is found to have occurred, the receiver resorts to LMMSE estimation processing.

Abstract: A method for designing an equalizer and tracking performance for upstream PCM in a digital communications network is described. The invention optimizes upstream data rate rates for data transmissions in a network between a client modem a server modem. During training, the upstream channel impulse response is identified compensating for any robbed bit signalling. The upstream transmit equalizer is computed in closed form based on the identified channel. An equalizer in the receiver is also used to track timing and channel variations. The invention approximates bit error rate performance by looking for code violations in the trellis code decoder and tracking their frequency. The bit error rate is used to determine if the current modem parameters need to be re-designed.

Abstract: The invention presents a software agent that optimizes processing resources for multiple instances of a software module that are executing simultaneously. The agent allocates and distributes processing resources, such as MIPS (millions of instruction cycles per second), to software functions executing on a core and controls resource distributions and module functions in a manner such that maximum processing capacity is utilized but not exceeded. The agent schedules the enabling and disabling of software module instance functions using a prioritization scheme that allocates MIPS to functions as the functions are enabled. An exemplary embodiment optimizes MIPS resources for multiple instances of an echo cancellation unit operating on a DSP (digital signal processor) core.

Abstract: A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one side of the member to close one end of each aperture. After devices are inserted into the apertures with their first ends “up” and their second ends “down,” a second removable cover is attached to the other side of the member to close the other end of each aperture. After inverting the assembly, removal of the first cover presents the devices in the apertures with their second ends “up” and their first ends “down.

Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.

Abstract: A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bit indicates the power-up state and a reset mode if the bit indicates a power-down state. Return to normal mode is delayed a predetermined time after the said bit of indicates the power-up state to ensure clean power up. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the corresponding bit indicates the power-down state.

Abstract: A greater likelihood decoder, a method of deriving a reduced substreams maximum likelihood (RSML) decoded symbol vector and a multiple-input, multiple-output (MIMO) receiver incorporating the decoder or the method. In one embodiment, the decoder includes: (1) a suboptimal decoder that analyzes a received symbol vector to generate substream indicators and a decoded symbol vector estimate, (2) weakest substreams decision logic, coupled to the suboptimal decoder, that receives the substream indicators and selects weakest ones thereof and (3) subspace search logic, coupled to the suboptimal decoder and the weakest substreams decision logic, that further selects a reduced substreams maximum likelihood (RSML) decoded symbol vector from a subspace of decoded symbol vector candidates derived from the decoded symbol vector estimate and the weakest ones.

Abstract: An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB value. The desired dB value is selected from a set having an integer number S of dB values. The system also comprises a storage circuit (16) for storing an integer number V of linear gain values and circuitry for producing a linear gain signal (LG) in response to the gain index signal and to one of the V linear gain values. In the preferred embodiment, V is less than S.