Abstract: A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of Y, U and V according to the prediction unit size of the coding unit.

Abstract: A semiconductor system (100) has a first planar leadframe (101) with first leads (102) and pads (103) having attached electronic components (120), the first leadframe including a set of elongated leads (104) bent at an angle away from the plane of the first leadframe; a second planar leadframe (110) with second leads (112) and pads (113) having attached electronic components (114); the bent leads of the first leadframe conductively connected to the second leadframe, forming a conductively linked 3-dimensional network between components and leads in two planes; and packaging material (140) encapsulating the 3-dimensional network.

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.

Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

Abstract: A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for every pixel intensity value to form display data codeword tables so that there are at least as many display data codeword tables as the number of display data bits with substantially equal time weights. The display pixel is subsequently operated in a digital manner according to the display data codeword in the selected display data codeword table to display a desired pixel intensity value. The display data codeword tables are configured so that immediately adjacent display pixels are operated so that identical pixel intensity values are displayed with different temporal sequences.

Abstract: The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a transistor switch coupled between the switch node and ground. The boost stage includes a boost inductor coupled between an input supply voltage and the switch node, and the charge pump stage includes a charge pump capacitor coupled between the switch node and a pump node which is coupled to the load and an output capacitor in parallel with the load.

Abstract: An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract: The present disclosure provides a receiver, a transmitter and methods of operating a receiver and a transmitter. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter, having multiple transmit antennas, that is capable of transmitting at least one spatial codeword and adapting a transmission rank. The receiver also includes a feedback generator portion configured to provide a channel quality indicator that is feedback to the transmitter, wherein the channel quality indicator corresponds to at least one transmission rank.

Abstract: An apparatus includes a vapor cell having multiple cavities fluidly connected by one or more channels. At least one of the cavities is configured to receive a first material able to dissociate into one or more gases that are contained within the vapor cell. At least one of the cavities is configured to receive a second material able to absorb at least a portion of the one or more gases. The vapor cell could include a first cavity configured to receive the first material and a second cavity fluidly connected to the first cavity by at least one first channel, where the second cavity is configured to receive the gas(es). The vapor cell could also include a third cavity fluidly connected to at least one of the first and second cavities by at least one second channel, where the third cavity is configured to receive the second material.

Abstract: A mobile wireless device that includes a positioning system to determine a position of the mobile wireless device and to compensate a received signal strength indicator (RSSI) signal received from an access point (AP) when there is a line-of-sight (LOS) channel and the positioning system determines the body of the user of the mobile wireless device is attenuating the received RSSI signal due to the user's body being between the mobile wireless device and the AP.

Abstract: For crest factor reduction in a first signal having first and second components, the first component is delayed. A second signal is generated in response to detecting that a peak in the first component exceeds a predetermined threshold. Amplitude of the peak in the first component is reduced in response to detecting that the peak in the first component exceeds the predetermined threshold. Reducing amplitude of the peak in the first component includes adding the second signal to the delayed first component.

Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.

Abstract: A first apparatus includes a vapor cell having first and second cavities fluidly connected by multiple channels. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity. A second apparatus includes a vapor cell having a first wafer with first and second cavities and a second wafer with one or more channels fluidly connecting the cavities. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity.

Abstract: A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin?) and the second control terminal.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.