Abstract: A method of performing a pattern fill operation of a pattern into a clipping region divides dividing the pattern into a plurality of bands. For each band the method renders the band as a bit map into a band cache. For each tiling of the pattern into the clipping region the method clips the bit map of a current band to the clipping region and copies the clipped bit map into a corresponding location of a page bit map. The plurality of bands of the pattern are preferable aligned with scan lines of the printed page. The bands may correspond to individual scan lines. The method select the number of bands so that each band may be stored within a predetermined amount of band cache memory.

Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).

Abstract: An electrostatic discharge (ESD) device for protecting a power amplifier circuit is disclosed. The ESD device comprises a first ESD protection circuit coupled between a positive terminal of a supply voltage and a negative terminal of the supply voltage, and a second ESD protection circuit coupled between the negative terminal of the supply voltage and an output terminal of the power amplifier circuit, wherein a first current path is formed from the positive terminal to the output terminal through the first and second ESD protection circuits. A circuit device operative to increase impedance of a second current path from the positive terminal to the output terminal through the power amplifier circuit to divert current from the second current path to the first current path in the course of an ESD event.

Abstract: The fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second 5-transistor transconductor having a common mode node coupled to the common mode node of the first 5-transistor transconductor, wherein the second 5-transistor transconductor operates 180 degrees out of phase with the first 5-transistor transconductor.

Abstract: An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM) output signal that varies between first and second rails based on a first control input signal, and a common mode supply that provides a switching signal that varies between third and fourth rails to maintain a common mode voltage of the load at a level that is between the first and second rails.

Abstract: A system for, and method of, text-to-phoneme (TTP) mapping and a digital signal processor (DSP) incorporating the system or the method. In one embodiment, the system includes: (1) a letter-to-phoneme (LTP) mapping generator configured to generate an LTP mapping by iteratively aligning a full training set with a set of correctly aligned entries based on statistics of phonemes and letters from the set of correctly aligned entries and redefining the full training set as a union of the set of correctly aligned entries and a set of incorrectly aligned entries created during the aligning and (2) a model trainer configured to update prior probabilities of LTP mappings generated by the LTP generator and evaluate whether the LTP mappings are suitable for training a decision-tree-based pronunciation model (DTPM).

Abstract: A system for, and method of, developing high accuracy acoustic models and a digital signal processor incorporating the same. In one embodiment, the system includes: (1) an acoustic model initializer configured to generate initial acoustic models by seeding with seed monophones, (2) a monophone retrainer associated with the acoustic model initializer and configured to retrain the monophones using a target database, (3) a triphone generator associated with the monophone retrainer and configured to generate seed triphones from the monophones using aligned training data, (4) a triphone retrainer associated with the triphone generator and configured to retrain the triphones using the target database and (5) a triphone clusterer associated with the triphone retrainer and configured to cluster the triphones using a state-tying technique, the triphone retrainer configured to retrain the triphones again using the target database.

Abstract: The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor substrate, subjecting the stress inducing layer to a first temperature anneal, and subjecting the semiconductor substrate to a second temperature anneal subsequent to the first temperature anneal, wherein the second temperature anneal is higher than the first temperature anneal.

Abstract: System and method for reducing interference to existing devices. A preferred embodiment comprises specifying a frequency range for a set of dummy signals, specifying a clipping function to ensure that the set of dummy signals do not exceed a maximum power constraint, incorporating a least squares solution for computing the set of dummy signals into the clipping function, and iterating the clipping function until a terminating condition is reached. The use of the clipping function limits the magnitude of the dummy signals, to ensure that dummy signals do not exceed a maximum power constraint.

Abstract: In a voice activity detection (VAD) device a method for defining tone signals comprises defining a threshold for zero amplitude change, calculating a zero crossing rate of a signal, extracting a set of parameters from a plurality of duration periods of the signal, defining a tolerance threshold between the plurality of duration periods when a zero amplitude change occurs, calculating a maximum difference between the plurality of duration periods, and comparing the maximum difference with the threshold. The method is implemented in the International Telecommunications Union (ITU) recommendation G.729 Annex B VAD.

Abstract: A voltage supply circuit which suppresses generation of current spikes in the power source current in operation, reduce noise, simplify the circuit configuration, and decrease the cost. Clock signal CLK at a prescribed frequency is supplied to charge pump driver (10); current sources IS1, IS2, . . . IS6 work at timing set with clock signal CLK to output driving currents; and, corresponding to the driving currents, capacitors C1, C2 . . . are alternately charged or discharged; the charge stored in the capacitor of a preceding stage is sequentially sent to the later capacitor stage, and a boosted voltage higher than power source voltage Vcc is obtained at output terminal T2. In the charge pump type booster, since capacitors are driven with current sources, it is possible to reduce spike noise in the boosting operation, and influence on other analog circuits can be suppressed.

Abstract: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

Abstract: A multi-carrier communications system with a programmable interleaver and de-interleaver that can change the interleaving rate for data transmitted and received in the communications system is presented. The programmable interleaver and de-interleaver permits a level of flexibility in determining the immunity of the communications system to errors and sources of interference. The multi-carrier communications system is able to vary the interleaving rate based on input from a user or from data that it maintains from actual network performance. The multi-carrier communications system can change the interleaving rate during the initial installation of the multi-carrier communications system or whenever the system is reset or restarted or on any individual transmission unit.

Abstract: The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and tasks associated with each transition. An execution block iteratively (in loops) transitions between the states according to the FSM representation, performing various operations according to the specified tasks in the transitions. In an embodiment, each state is associated with utmost one file providing inputs to the application. Such an approach provides an explicit control flow and easier way to develop and manage an application.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: In digital communications that utilize a data packet format wherein each data packet includes a physical layer (PHY) component and a media access control layer (MAC) component, the media access control layer component can be selectively protected by forward error correction (FEC). The receiving end receives an indication as to whether FEC has been applied, and makes an FEC decision based (12-15) on this indication. The accuracy of the received-side FEC decision and the robustness of the FEC indication can be improved by: making the FEC decision based on the results of FEC decoding applied to a media access control layer header within the media access control layer component; providing an FEC indication bit in the physical layer component; and using a plurality of bits to encode the FEC indication in either the physical layer component or the media access control layer component.

Abstract: Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

Abstract: An integrated circuit including a precharge circuit for a DC/DC boost converter which includes a reference current circuit with a MOSFET transistor (MP4) that has a gate connected with the gate of the DC/DC boost converter's power MOSFET transistor (MP5) to form a current mirror. The precharge circuit works to approach the output voltage to the supply voltage prior to the converter startup. An included regulation circuit adjusts the gate potential at the power MOSFET transistor (MP5) and at the MOSFET transistor (MP4) in the reference circuit in response to a reduction of the drain-source voltage of the power MOSFET transistor (MP5) due to precharging load capacitance, in a sense to keep the precharge current through the power MOSFET transistor (MP5) constant.

Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.