Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summer, and a current-controlled oscillator (CCO). The phase frequency detector detects a frequency difference and a phase difference between a clock signal and a comparison signal, communicates the frequency difference to a first charge pump generating a first current, and communicates the phase difference to a second charge pump generating a voltage. The comparison signal is derived from an output signal of the PLL. The first charge pump modifies the first current according to the frequency difference and communicates the first current to the current summer. The second charge pump modifies the voltage according to the phase difference and communicates the voltage to the V2I converter.

Abstract: Determining the transition counts at various scan elements of a scan chain (for sequential scan tests) by merely examining the bits of an input vector and the expected results of evaluation. In an embodiment, assuming there are N bits of input vector (with the Nth bit being scanned in first and first bit being scanned in last) and N elements of a scan chain (with the first scan element receiving each bit first), the number of transition at Nth scan element equals an XOR of the Nth bit and the bit stored in the first scan element before scan-in operation. The number of transitions at Pth scan element then equals a sum of (XOR of (P+1)st bit and (Pth bit)) and the number of the transitions at the (P+1)st element. The transitions due to scan out operations can also be similarly determined. The computed number of transitions can be used for determining power dissipation during sequential scan test.

Abstract: An integrated circuit including a precharge circuit for a DC/DC boost converter which includes a reference current circuit with a MOSFET transistor (MP4) that has a gate connected with the gate of the DC/DC boost converter's power MOSFET transistor (MP5) to form a current mirror. The precharge circuit works to approach the output voltage to the supply voltage prior to the converter startup. An included regulation circuit adjusts the gate potential at the power MOSFET transistor (MP5) and at the MOSFET transistor (MP4) in the reference circuit in response to a reduction of the drain-source voltage of the power MOSFET transistor (MP5) due to precharging load capacitance, in a sense to keep the precharge current through the power MOSFET transistor (MP5) constant.

Abstract: A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to a write/search driver and one or more precharge circuits. In one example embodiment, this is accomplished by precharging each read/write bit line substantially after completing a read cycle using the one or more precharge circuits. Then, precharging each read/write bit line substantially after completing a write cycle using a write/search bit line decoder and driver circuit, followed by precharging each search bit line in the CAM block array using the write/search bit line decoder and driver circuit substantially after completing a search operation.

Abstract: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Abstract: A wireless device containing a physical layer (in a transceiver) which generates multiple status signals indicating the status of the wireless medium at different time instances. The status signals are examined to determine a time instance after which the medium is available to transmit the packets. In an embodiment, one status signal indicates whether valid preamble bits are being received on (before end of the preamble) the wireless medium consistent with the 802.11a standard and another status signal indicates similar status but for 802.11b standard. The embodiment further includes a qualification logic, which determines a time instance after which the availability of medium is determined.

Abstract: An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital interface circuit includes a plurality of data inputs, at least one control input, at least one clock input, and a single serial bit output. The digital interface circuit receives respective input data streams at the data inputs, receives digital control information at the control input, and receives a clock signal at the clock input. The control information is an N-bit data stream having a data rate of 1/N times the rate of the input data streams (N?1). The digital interface circuit generates a frame synchronization signal for providing framing for the N-bit data stream, and time-multiplexes the data and control information over the single serial bit output.

Abstract: A method is provided to provide data to automatically estimate channel performance in a communication system if a different order constellation is used comprising the steps of: receiving an input signal from the channel; passing the input signal to a slicer having an output signal; determining signal noise by taking the difference between the input signal and output signal; identifying a beginning of a noise event when the signal noise is greater than a predefined first threshold; identifying an end of a noise event when the signal noise is less than a predefined second threshold; and providing for output the beginning of the noise event and the end of the noise event. Other systems and methods are disclosed.

Abstract: A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first voltage-to-current converter that converts the voltage received at a first input to a first current, and a second voltage-to-current converter that converts a voltage signal received at a second input to a second current. A current subtractor provides a difference current of the first and second currents that is indicative of the differential signal.

Abstract: In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.

Abstract: A distributed web CGI architecture is disclosed. According to one embodiment of the present invention, distributed web common gateway interface architecture includes a primary network having a primary server (304). A database (210) communicates with the primary server (304). A plurality of secondary networks (202) are provided, with at least one secondary server (302) in the secondary network (202). In another embodiment, a method for the distribution of data files in a distributed organization is provided. The distributed organization has a multiple networks that communicate with the primary server. The method involves the steps of (1) validating a data file at a secondary server in one of the networks; (2) correcting defects in the data file if the validation fails; (3) releasing a validated data file to the primary server; (4) and transferring the validated data file to the primary server.

Abstract: Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum (24-29). An available resource map (ARM) contains resource availability information gathered by mobile stations (MS1-MSn), and a wired communication channel supports sharing of resource control information among fixed-site stations (BS).

Abstract: A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated circuit) are designed. In an embodiment, a designer specifies various checkpoints associated with each design stage, and the specific information to be made available to a top level performing the validation. When each checkpoint is reached for a design block, the specified information is made available to the top level and the validation of the integrated circuit is performed up to that checkpoint. As a result, design closure of the integrated circuit can be obtained quickly.

Abstract: A dual path equalization structure is used to equalize DMT systems operating over channels in which different impairments dominate the performance of different parts of the channel. Two TEQ/DFT structures are used to process the received signal, each optimized for a different part of the channel. The outputs of the two paths are combined with appropriate frequency-domain equalization to achieve an overall equalization architecture which is better optimized for the whole channel.

Abstract: The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

Abstract: A communication device (e.g., a modem) is disclosed as including logic that processes a transmit signal before providing a signal to an echo canceler. The processing may include low pass filtering and decimation of the transmit signal. The low pass filter's cut-off frequency preferably is less than the sampling rate associated with the transmit signal.

Abstract: The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).

Abstract: Methods and apparatus are provided for preventing charge accumulation in microelectromechanical systems, especially in micromirror array devices having a plurality of micromirrors. Voltages are applied to the micromirrors for actuating the micromirrors. Polarities of the voltage differences between mirror plates and electrodes are inverted so as to prevent charge accumulation.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.