Abstract: The present invention provides a spurious tone suppressor for use with a power supply system. In one embodiment, the spurious tone suppressor includes an error signal generator configured to provide a spur error signal proportional to a spur signal associated with the power supply system. Additionally, the spurious tone suppressor also includes an adaptive spur cancellation engine coupled to the error signal generator and configured to adaptively process the spur error signal and generate a corresponding anti-spur signal that is injected into the power supply system to suppress the spur signal.

Abstract: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Abstract: Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a common mode replica stage, and an amplifier is disclosed. The differential input stage exhibits an input common mode, and includes two differential inputs. A signal from the differential input stage representing the input common mode is electrically coupled to an input of the amplifier. Another input of the amplifier is electrically coupled to the common mode replica stage, and the amplifier outputs a signal indicative of the input common mode.

Abstract: A wireless handset having the capability of browsing full Internet web pages is disclosed. The handset includes a position sensing device, such as an optical sensor or a mouse ball and rollers, at its bottom surface. In an Internet browsing operating mode, a portion of a web page is displayed on a graphics display of the handset. Movement of the handset along a solid surface, similar to the movement of a computer mouse, will change the portion of the web page displayed. A cursor is displayed over the web page, and handset keys correspond to “left-click” and “right-click” functions in this mode. In a text entry mode, a portion of a keyboard layout is displayed, so that selection of characters using the cursor and movement of the handset is effected.

Abstract: A mirror display system comprising a multiplicity of scan lines that are combined to generate an image. The multiplicity of scan lines are orthogonally positioned in response to a slow speed cyclic drive signal (for example, sinusoidal or repetitive triangular shape). To increase the brightness of the display, and unlike a typical raster scan display, scan lines are generated during both the positive going portion and the negative going portion of the cyclic drive signal.

Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

Abstract: Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.

Abstract: A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.

Abstract: Correcting a mask pattern includes accessing the mask pattern segmented into segments. An attribute value is established for each segment, where the attribute value for a segment describes an attribute of the segment. The following is repeated for one or more of the attribute values to generate a corrected mask pattern: selecting segments using one or more attribute values; calculating a current correction value for each of the selected segments with respect to previously selected segments updated according to previously calculated correction values; and updating the selected segments according to the current correction values.

Abstract: The present invention provides, in one aspect, a method of imaging a microelectronics device 100. The method comprises cleaning, when contaminants are preset, a sample of a microelectronics device 100 to be imaged with a first solution comprising hydrofluoric acid, an inorganic acid and water, exposing the sample to a second solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the second solution forms a contrast between different regions within the sample, and producing an image of the contrasted sample.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: As robust hinge post structure for use with torsional hinged devices such as micromirrors and method of manufacturing is disclosed. The fabrication process uses a protective layer such as BARC on the bottom of the aperture used to form the hinge post structure to protect an oxide layer during an etching step. The oxide layer, in turn protects the metal layer at the bottom of the aperture. Therefore, the metal layer, the oxide layer, and the protective layer prevent the erosion and/or pitting of the bottom electrode during a cleaning process, and provide additional support to the structure.

Abstract: A Class-D amplifier system may include an input stage that includes an Nth order filter, where N>1. The input stage filters an input signal to provide a filtered output signal, an input of the input stage being configured to receive the input signal as a digital pulse-width-modulated (PWM) signal. A comparator provides a quantized output signal based on the filtered output signal. An output stage is connected between a first voltage rail and a second voltage rail. The output stage provides a switching output signal at an output that varies between the first voltage rail and the second voltage rail based on the quantized output signal. A feedback path connects the output of the output stage with the input of the input stage, such that the Nth order filter compensates for variations in at least one of the first voltage rail and the second voltage rail.

Abstract: A method is provided for equalization of nonlinear distortion in a distorted signal comprising the steps of: digitizing the distorted signal and passing the digitized distorted signal through an inverse non-linear transfer function to equalize the nonlinear distortion. Other systems and methods are disclosed.

Abstract: A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Abstract: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device interface board. The area of the at least one output orifice is substantially greater than the area of input orifice.

Abstract: In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection optics, in the present invention, micromirrors are provided which are not rectangular. Also, in order to minimize the cost of the illumination optics and the size of the display unit of the present invention, the light source is placed orthogonal to the rows (or columns) of the array, and/or the light source is placed orthogonal to a side of the frame defining the active area of the array. The incident light beam, though orthogonal to the sides of the active area, is not however, orthogonal to any substantial portion of sides of the individual micromirrors in the array. Orthogonal sides cause incident light to diffract along the direction of micromirror switching, and result in light ‘leakage’ into the ‘on’ state even if the micromirror is in the ‘off’ state. This light diffraction decreases the contrast ratio of the micromirror.