Abstract: A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

Abstract: A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each channel has a channel order (L). A first method includes precomputing, from the long sequence (X) of a received signal, a channel estimation matrix (R?1) having a dimension of width and length equal to the channel order (L) and storing one fourth of the channel estimation matrix (R?1) since the channel estimation matrix (R?1) is centrosymmetric. Advantageously, precomputing and storing a fourth of the channel estimation matrix (R?1) saves time and complexity. In a second method, the bit-width requirement for fixed precision requirements regarding implementation in hardware is reduced wherein a channel estimation matrix (G) having dimension of width equal to the number of tones (N) and length equal to the channel order (L) is precomputed and stored.

Abstract: According to one embodiment a method for aligning a light source includes providing a lamp and a lamp interface. The lamp interface has an alignment aperture disposed thereon. The method also includes aligning the lamp with respect to the lamp interface until a desired amount of light is focused on the alignment aperture. The method further includes fixing the lamp to the lamp aperture to form an aligned lamp assembly after obtaining a desired lamp alignment. Then the aligned lamp assembly is coupled to an integrating rod.

Abstract: Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

Abstract: A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Abstract: Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an output connected to a serial data output lead. A first gate has an output connected to the control input of the first buffer, a scan output enable input connected to a scan circuitry control output lead, and a lock out signal input. A second buffer has an input connected to a test data output lead, an input connected to a buffer enable output lead, and an output connected to a serial data output lead. This structure provides for selecting data outputs between the TAP and internal scan test ports.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a plurality of user (USER) bits. The transmitter also comprises circuitry for modulating (16) the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter also comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points, and selected (SF2.x) OFDM symbols in the serial stream of OFDM symbols carry modulation information (AMOD).

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated circuit (42) includes a circuit (61) for selectively operating the integrated circuit (42) in either a voltage or a charge mode of operation. A first amplifier circuit (44) can be compensated for a variable number of piezo elements in the charge mode of operation by adjustable output impedance adjusting elements (124, 126, 138-141) that are switchably connectable into the amplifier circuit (44).

Abstract: System and method for improving performance of digital wireless communications systems in the presence of interferers. A preferred embodiment comprises generating a list of hypotheses from a list of known interferers and timing offsets, receiving a signal transmitted over-the-air, computing an error variance for each hypothesis, and selecting the hypothesis with the lowest error variance. The hypothesis can then be used to extract data from the received signal.

Abstract: The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level. When the reference level is crossed the pixel is reset. This process is repeated several times in a given frame time cycle with the reference level steadily decreasing. The various reset times represent the light intensity on the pixel. For an image sensor array, the array is scanned multiple times during one image frame time cycle and the reference level is lowered each scan. This provides an image sensor that has built-in pixel non-uniformity suppression, digital output, and high sensitivity.

Abstract: System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.

Abstract: The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception. In one embodiment, the offset balancer includes an offset adjuster coupled to the offset quantifier and configured to provide an offset adjustment to the existing DC offset based on increasing the existing second-order intercept point.

Abstract: Various systems and methods for LCD backlight control are disclosed herein. For example, some embodiments of the present invention provide an LCD backlight circuit with an analog inverter circuit that provides a drive voltage to a lamp. A current traversing the lamp is sensed and provided to a digital control circuit. Based on the sensed current, the digital control circuit generates a control signal that is fed back to the analog inverter circuit. In some cases, the digital control circuit is used to cause a gradual increase in voltage applied to the lamp to achieve ignition of the lamp. In other cases, the digital control is used to provide a pre-distorted sine wave that attenuates one or more harmonics introduced into the system by the non-linearities of the lamp.

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract: The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

Abstract: Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state 310. Accordingly, one method 500 comprises powering-up 510 the memory device and reading 520 a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method 500 then captures and stores 530 a data state associated with the preferred power-up data state of each cell 100 and utilizes the stored power-up data state 310 or an inverse of the power-up data state 320 to tailor 540 a test pattern used by the test algorithm 460.

Abstract: A system and method of varying the control loop gain of an optical wireless communication link between a transmitting station and a receiving station as an inverse function of distance between the transmitting station and the receiving station to allow the optical wireless communication link to be used reliably over a wide range of distances.

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.