Abstract: The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that generates transient response OUT2 in a second polarity direction opposite to the first polarity, and a transient response synthesizing circuit 6 that combines the transient response OUT1 in the first polarity direction and the transient response OUT2 in the second polarity direction to generate composite transient response OUTC.

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract: A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906). The bond pads on the electrical device (906) are electrically connected to bond pads on the package (904) by a series of bond wires (908) through use of a well know bonding process. A vacuum source holds the package (904) against the pedestal (902) deforming the resilient strips (920) located in the rigid member (902) of the pedestal and ensuring good contact between the ground pads of the package (904) and conductive resilient members (920). The resilient members (920) are conductive and electrically connect the package grounds to a system ground (922).

Abstract: A method and apparatus for operating spatial light modulator have been disclosed herein. The spatial light modulator comprises an array of micromirror devices, each of which further comprises a reflective deflectable mirror plate attached to a deformable hinge, and an addressing electrode for addressing and deflecting the mirror plate.

Abstract: A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be deposited over the resistor material (104). The resistor material (104) and hard mask material (106) are patterned and sputter etched to form the resistor body. For example, a sputter etch chemistry comprising BCl3, Cl2, and Ar may be used to etch the resistor material.

Abstract: An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage through a first impedance circuit. A p-type transistor of the circuit has a source coupled to the source of the n-type transistor, a gate coupled to a second bias voltage, and a drain coupled to a second supply voltage through a second impedance circuit. A first differential input is coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor. A second differential input is coupled to the sources of the n-type and the p-type transistors. A third capacitor has a first end coupled to the drain of the n-type transistor, and a fourth capacitor has a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor. An output of the amplifier circuit is provided at the second ends of the third and the fourth capacitors.

Abstract: A system for providing a threshold voltage (VT) includes a VT extractor that extracts the VT for a MOS transistor relative to a first voltage rail. An inversion circuit inverts the extracted VT (e.g., VT+VIN) relative to a reference voltage that is intermediate the first voltage rail and a second voltage rail and provides an output corresponding to the VT (e.g., VT+VIN) relative to the second voltage rail. The relative voltages at the voltage rails generally will depend on whether the VT is being extracted for a p-channel MOS transistor or an n-channel MOS transistor. The VT can be employed to generate a ramp voltage across a capacitor formed of another MOS transistor.

Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (51) are established, at which received ATM cell payload data may be stored. An ATM receive controller (134) is provided in the USB interface device (30), which receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine which, if any, virtual connection the cell corresponds. The ATM receive controller (134) then forwards the payload portion of the ATM cell, but not the ATM cell header, to the endpoint (51) corresponding to the virtual connection to which the ATM cell is directed. The disclosed ATM receive controller (134) also includes logic (64) for calculating a cyclic redundancy check value over the payload portion of the ATM cells that make up an ATM packet.

Abstract: One embodiment of the present invention may include a programmable gain amplifier comprising an input multiplexer operative to sequentially select input signals for amplification. The input signals may be chosen from a plurality of input signals based on a selection signal. The programmable gain amplifier may include at least one amplifier gain stage operative to apply a variable gain amount to a selected input signal. The programmable gain amplifier may further include a gain mapping component that controls the variable gain amount for each of the selected input signals.

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.

Abstract: The distance between a first Multi Band Orthogonal Frequency Division Multiplex (MB-OFDM) data transceiver and a second or more such transceiver is determined using known techniques. The radio frequency path loss between transceivers is estimated given said distance, using a known relationship between distance and path loss, and further accounting for line-of-sight or non-line-of-sight conditions if desired. This path loss value is added to the typically minimum transmit power level, absent path loss, needed for reliable data communication. This modified initial transmit power level is then used by the first transceiver to begin the known iterative feedback process of transmit power control (TPC). Because this modified initial transmit power level, based on distance, is closer to the final optimum level, convergence in the TPC process occurs in fewer steps and less time than had the initial transmit power been maximum power as is typical in known TPC systems.

Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations.

Abstract: A router includes a transceiver operable to transmit and receive packets when operably connected to a communication network, and a processor cooperatively operable with the transceiver. The processor is associated with a unique network routable value and/or a physical address. The processor is configured to facilitate receiving a packet in accordance with the transceiver. The processor checks the packet for an indication to determine if the unique network routable address value and/or the physical address are to be inserted in a router location information field in the packet. If the packet has the indication, the processor inserts router location information indicative of the unique network routable address value and/or the physical address in the packet. The processor transmits the packet in accordance with the transceiver.

Abstract: An energy consumption meter having a variable phase error compensator. While the variable phase error compensator may provide fixed phase error compensation for fixed phase error(s), it may also provide variable compensation for varying phase error(s) introduced by one or more parameters. Varying phase error(s) may be introduced, for example, by fluctuations in the frequency of an alternating current supply. Such varying phase errors may be corrected by monitoring one or more sources of varying phase error(s), calculating one or more appropriate corrections, and correcting one or more sampled parameters involved in determining energy consumption. This avoids erroneous energy consumption metering due to varying phase errors.

Abstract: The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Abstract: A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is operative to reduce the requirements for or completely eliminate the need for the anti-aliasing filter by dynamically modifying the sub-sampling rate (or decimation ratio). Rather than maintain a constant sampling rate (or decimation ratio), the sampling rate (or decimation ratio) is randomized such that its average remains at the nominal value and the effective jitter is low enough for the low rate (or low decimation ratio) system to tolerate. This smears or spreads interfering signals across the spectrum resulting in a noise floor at a significantly reduced level much lower than that of the original interferer signal. The interfering signals are reduced to background noise wherein the level of the resulting noise floor is not nearly as strong as the original interfering signal.

Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.