Abstract: An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.

Abstract: A method and a color rendering filter for compensating for deficiency in illumination light from a light source in display systems are provided. The color rendering filter has a color that is determined based upon the spectrum, sensitivity of viewer's eyes over the visible light range, and a pre-determined waveband threshold.

Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor (811), preferably about 10 k?, connected to the discharge circuit, and a control MOS transistor (812) in series with the discharge resistor. The transistor source (812a) is connected to the resistor, the drain (812b) to ground, and the gate (812c) to core power (813) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: The objective of this invention is to prevent the generation of defects pertaining to placement of solder balls on the terminal placement parts of the electronic part main body. The solder ball 1 has spherical core 2 and coating layer 3 that covers core 2. The coating layer 3 contains a resin. The diameter of core 2 is in the range of 30-500 ?m. The thickness of coating layer 3 is in the range of 5-100 ?m. The coating layer 3 is melted at temperature in a range of 20° C. between 150 to 300° C., and the viscosity of coating layer 3 is in the range of 0.01-50 Pa-s. After solder balls 1 are set on terminal placement parts 13a in the main body of the electronic part, reflow is performed for solder balls 1. As a result, coating layer 3 is melted first, and core 2 descends under its own weight to come into contact with the terminal placement part. Core 2 is then melted, and core 2 and terminal placement part 13a are soldered and joined to each other.

Abstract: Communications systems are disclosed which comprise system and methods which, in some embodiments, include a data input; a decoding function, which is adapted to receive a first data element and a second data element from the data input and decode the first data element and second data element, and a mapping element, which is adapted to map the first data element and second data element onto two constellations.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Abstract: A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output pulses 4 toggled as desired. Also a circuit 1 for evaluating an output 4 of a sequential circuit 2 that determines if the output pulses 4 toggled as desired.

Abstract: A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of differential inputs and at least one differential output. The multiplexor includes a plurality of transmission gates to allow any one of the differential inputs to be routed to any differential output. Each transmission gate includes a first PMOS transistor and an NMOS transistor. The multiplexor further includes first Schottky diodes coupled between Vcc and the back-gate nodes of the first PMOS transistors, and second PMOS transistors coupled as shunts between the gate nodes of the first PMOS transistors and the source nodes of the NMOS transistors.

Abstract: An amplifier providing a drive signal indicative of a data input signal to a capacitive and/or resistive type load, the amplifier having a first transistor circuit adapted for converting the data input signal to a corresponding current signal in which the transistors of the first transistor circuit operate at a first voltage and having a second transistor circuit amplifying the current signal in which the transistors of the second transistor circuit operate at a second voltage. The first transistor circuit and the second transistor circuit are integrated for providing a class AB operable current output to the load.

Abstract: A method and apparatus provide phase, frequency and gain characterization and mitigation in a synchronized code division multiple access (SCDMA) burst receiver via use of dedicated phase and frequency correction loops that implemented to deal with the unique characteristics of a SCDMA signal. The way coded and un-coded bits are interleaved within a given frame requires that all symbols related to that frame be captured in a dedicated storage medium such as a RAM prior to the beginning of the data processing. The method and apparatus substantially eliminate gain, phase, and frequency, among other impairments caused by the transmitter, channel and analog parts of the SCDMA burst receiver.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2).

Abstract: A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract: The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

Abstract: A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.