Abstract: A method for coating free-standing micromechanical devices using spin-coating. A solution with high solids loading but low viscosity can penetrate the free areas of a micromachined structure. Spinning this solution off the wafer or die results in film formation over the devices without the expected damage from capillary action. If an organic polymer is used as the solid component, the structures may be re-released by a traditional ash process. This method may be used as a process in the manufacture of micromechanical devices to protect released and tested structures, and to overcome stiction-related deformation of micromechanical devices associated with wet release processes.

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry (DI) is connected to the memory circuit for indicating if data within the cache is incoherent with a secondary back-up memory. DMA circuitry can transfer (1652) blocks of data/instructions (1660) between the cache and a secondary memory (1602). A transfer mode circuit (1681) controls how DMA operations are affected by the dirty bits. If the transfer mode circuit is in a first mode, a DMA operation transfers only segments (1661) indicated as dirty (1685). If the transfer mode circuit is in a second mode, a DMA operation transfers and entire block of data (1660) without regard to dirty indicators (1686).

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A trigger signal TRIG[0] is produced for use in debugging data processor (14) operations. The trigger signal can be generated in response to event information indicative of events associated with operations of the data processor and further in response to past behavior of a trigger signal. A plurality of intermediate terms index into a look up table loaded from a trigger builder control register. The look up table output is ANDed with output enable signals to produce plural trigger output signals.

Abstract: A printer controller for processing print data includes a data processor, direct memory access controller, first and second memories with corresponding first and second transfer data busses. A bus switch selectively connects the first and second data transfer busses. When uncoupled, the data processor accessed the said first memory via the first data transfer bus and the direct memory access controller may independently accesses the second memory via the second data transfer bus. When connected, either the data processor or the direct memory access controller may access either memory to the exclusion of the other. This permits better allocation of data transfer bandwidth in the memory controller.

Abstract: An apparatus (30) and method (80) for predicting electrical property stability of a thin film or conductive substrate (14) prior to multi-probe testing. The present invention utilizes a nanoindenter type device (10) obtaining mechanical properties as a function of displacement depth and applied load into the bond pad surface to accurately predict electrical property stability of the entire substrate or sample under test. In addition, the present invention includes a nanoindenter type device (10) including a second probe (34) having the ability to measure localized electrical properties of the sample while obtaining the mechanical property measurements. This additional electrical measurement is correlated with the mechanical property measurements to accurately predict electrical property stability of the entire conductive substrate, preferably by predicting the presence of an unwanted material surface layer.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).

Abstract: An upstream signal optimizer for use with a digital subscriber line (DSL) modem, a method of optimizing an upstream signal and a transmitter associated with a DSL modem. In one embodiment, the upstream signal optimizer includes (1) a signal adapter configured to shape a frequency domain of an upstream signal and (2) an adapter controller coupled to the signal adapter configured to control operation of the signal adapter based on a training sequence of the modem.

Abstract: The present invention is directed to a dual platform communication controller for use with a wireless communication system. In one embodiment, the dual platform communication controller includes a signal interpreter coupled to the wireless communication system and configured to recognize a first signal packet based on a first communication standard and a second signal packet based on a second communication standard. The dual platform communication controller also includes a traffic manager coupled to the signal interpreter and configured to provide a deterministic time-sharing between the first and second signal packets within the wireless communication system.

Abstract: A socket (10) has a base member (20), a cover member (30) which is mounted for alternating motion toward and away from base member (20), a plurality of contacts (40) having an end fixed to the base member (20), a contact regulating member (50) that regulates the position of the movable ends (42, 92) of the contact and an adaptor (60) having a seating surface, the adaptor which is mounted for alternating motion toward and away from the contact regulating member (50). When adaptor (60) is removed from the contact regulating member, the movable ends of the contacts do not protrude through the seating surface and when adaptor (60) has been moved toward the contact regulating member (50), the movable ends of the contacts protrude from each through-hole (65) of adaptor (60) for engagement with the solder balls of a BGA device (11), placed on the adaptor (60). The cover member is linked to the base member and latches (70) having a BGA device pressing tip (72) are rotatable with movement of the cover.

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer.

Abstract: The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system.

Abstract: A bit-interleaved encoder for a CATV upstream channel is provided having a convolutional encoder for receiving data values, a bit-interleaver interconnected with said encoder, and a symbol mapper interconnected with said bit-interleaver.

Abstract: A clipping circuit (20) for clipping an input signal to a level corresponding to a regulated power supply voltage (AVDD). The clipping circuit (20) includes a current mirror-like arrangement having a reference transistor (30) and a mirror transistor (32) The input signal (BDATA) is received at the drain of the mirror transistor (32), with the source of the mirror transistor (32) producing the output signal (CLPBDATA). The reference transistor (30) receives a bias current (IBIAS) that is mirrored by the mirror transistor (32) to limit the pull-up drive of the mirror transistor (32) in pulling up the output (CLPBDATA). Disclosed embodiments of the clipping circuit (20; 20′, 20″) include a current source (29) for producing a DC bias current (IBIAS), and a charge pump (34) for producing a transient bias current (IPUMP).

Abstract: This invention comprises an architecture for voltage mode control of a voice coil motor in a hard disk drive. In contrast to conventional current mode control, coil current is not sensed or measured, which simplifies the feedback design with less hardware required in the implementation. Common design methodologies for the square root velocity profile, linear velocity profile and regulator/estimator control system designs can be migrated from the current mode architecture to the voltage mode architecture.

Abstract: An image processing system comprising a burst memory; a data processor; and a data buffer coupled between the burst memory and the data processor. The data buffer comprises a block memory (81) coupled to the burst memory and to the data processor via a switch (83); and an access controller (82) coupled to the block memory (81), to the data processor and to the burst memory. The access controller (82) transfers data from the burst memory to the block memory (81) in a format specified to the access controller by the data processor via a first state of the switch (83). The access controller (82) also transfers the formatted data from the block memory (81) to the data processor via a second state of the switch (83). The format can comprise a block of data, a line of data, or data sampled from spatially diverse locations within a picture frame of data.

Abstract: An apparatus for providing optical black and offset calibration for an array signal comprising a sequence of voltage levels corresponding to a sequence of voltage samples of charge coupled devices arranged in an array. The apparatus includes a correlated double sampler adapted to receive the array signal and provide as an output a modified array signal comprising a sequence of first corrected output voltage levels. A programmable gain amplifier receives the modified array signal and provides as an output an amplified modified array signal comprising a sequence of second corrected output voltage levels. An analog to digital converter receives the amplified modified array signal and provides as an output a sequence of digital values. A digital signal storage device stores a digital value corresponding to a desired optical black level.

Abstract: A driving circuit reduces fall delay time, and the output timing of a driving current can be controlled highly accurately while reducing ringing during a transition of output current.

Abstract: An improved bump fabrication process is described that produces a larger diameter/taller solder ball than with a standard mushroom by forming an elongated mushroom having a short axis in the direction of adjacent connection mushrooms and an elongated axis orthogonal to the short axis. The increased larger volume solder when reflowed produces the larger diameter/taller bolder ball bump.

Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.