Abstract: Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.

Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A start up circuit includes: a diode Q0; a first transistor Q1 coupled in series with the diode Q0; a first resistor R4 coupled in series with the first transistor Q1; a second transistor Q2 having a control node coupled to a control node of the first transistor Q1 and coupled to a node between the first transistor Q1 and the first resistor R4; and a second resistor R2 coupled in series with the second transistor Q2 such that a current in the second transistor Q2 is independent of a voltage applied across the diode Q0, the first transistor Q1, and the first resistor R4.

Abstract: An exemplary method and circuit for temperature nonlinearity compensation and trimming of a voltage reference are configured to provide for two-point independent trimming of each of the curvature coefficients within the Taylor approximation curve. A voltage reference circuit is configured with a translinear circuit having an input current source. The translinear circuit comprises a translinear unit having a plurality of output currents corresponding to the curvature coefficients of the Taylor row approximation curve, with the output currents coupled to a control input terminal of the voltage reference. During trimming, at a first nominal temperature, the input current source is trimmed to a zero value, and each of the curvature terms of the Taylor approximation will be equal to zero value.

Abstract: The present invention provides for a method (30) and system (10) for isolating the input nodes (3, 4) and/or the output nodes (5, 8) of an analog device (12) and performing continuity testing thereof without using relays. The system includes an analog device having a pair of input and output terminals and a plurality of resistors (R1-R3 and R4-R6) arranged in parallel and connected thereto. The method for testing continuity of the analog device includes providing a voltage input via at least one of the resistors to either input node, and then measuring the voltage at the same node via a resistor. If a diode drop from ground is sensed there is continuity, and if the applied voltage is sensed at the node there is not continuity. As a result, the invention advantageously isolates the nodes and removes any unwanted capacitance and impedance loading thereon during testing thereof.

Abstract: The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements. Disclosed are the machine-implemented steps of defining the network in terms of a network value representing the sum of the elements. The network value is divided into an integer part and a proper fraction part. A partial quotient and residue are computed for the proper fraction part. Additional partial quotients and residues may be computed while the residue is significant. The physical implementation of the network is then described in terms of series and parallel elements represented by the integer part and the partial quotients. Also disclosed is a method of assembling a network from a combination of series and parallel elements. A network value consisting of an integer part and a proper fraction part are used to represent the network.

Abstract: A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

Abstract: A maximum length (M) of compressed codes desired to be decoded in a single lookup is determined. 2M rows are generated, with each row having a bit indicating whether a corresponding M-bit combination, when viewed from the first bit, contains a compression code and a source code corresponding to the compression code. A matching row corresponding to a value represented by M-bits of a source bit stream (“present portion”) is first determined, and the source code in the matching row is set as the decoded value if the matching row is indicated to contain a compression code. If the length (P) of the compression code corresponding to the decoded value is less than M, the last (M-P) bits of the present portion are used as a part of the next portion. Additional bits are used to generate the decoded value if the present portion does not contain the entire compression code.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Abstract: A wake-up circuit for a ECU on a CAN bus utilizes two complementary switching transistors which will turn ON when there is a differential voltage between CANH and CANL which will turn ON the transistors to pass a current which will be mirrored over to create a voltage which will switch a comparator or a Schmitt trigger. The two signals are then ORed together to generate a digital wake-up signal that can be utilized by other on-chip circuitry.

Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A switching power supply or switching regulator is provided with a control circuit that controls a switching signal to a first switch. The switching signal is also coupled to a second switch in an inverted state, such as the first and second switches are switched “ON” and “OFF” in opposing states. The first switch and the second switch are coupled through a common node. The second switch is also coupled to ground. An inductor is coupled to the common node and an output capacitor. The switching signal generates an operating current through the inductor that charges the output capacitor to provide a regulated voltage at an output terminal. The second switch is designed to handle the small reverse current that occurs when the first switch is turned off preventing the regulator from entering a discontinuous mode during light load conditions.

Abstract: A process for protecting a MEMS device used in a UV illuminated application from damage due to a photochemical activation between the UV flux and package gas constituents, formed from the out-gassing of various lubricants and passivants put in the device package to prevent sticking of the MEMS device's moving parts. This process coats the exposed surfaces of the MEMS device and package's optical window surfaces with a metal-halide film to eliminate this photochemical activation and therefore significantly extend the reliability and lifetime of the MEMS device.

Abstract: According to the present invention, there is developed a proprietary technology for compressing the window tables of audio coders to ⅛ their original size (or less) without any loss of quality. This technology can be applied to all transform based audio coders, or any audio coder that uses a windowing stage. The novel technique for reducing storage requirements for the window tables of audio coders is based on multiple differentiation. Since the difference between any two adjacent samples in the first difference signal is small, so it is more efficient to store this difference. This technique can be carried out several more times, until the returns get smaller, and the computational requirements to “undo” the compression go up. The optimum number of times to differentiate is dependent on the particular application and the window shape.

Abstract: A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with the first transistor MP4; an amplifier A1 having a first input coupled to the first and second transistors MP4 and MP3, and to a gate of the second transistor MP3, and a second input coupled to a control voltage node VCTRL; a third transistor MN4 coupled in series with the first transistor MP4; a fourth transistor MN2 coupled in series with the third transistor MN4 and having a gate coupled to an output of the amplifier A1; a fifth transistor MP1; a sixth transistor MP2 coupled in parallel with the fifth transistor MP1; a seventh transistor MN3 coupled in series with the fifth transistor MP1; and an eighth transistor MN1 coupled in series with the seventh transistor MN3 and having a gate coupled to a gate of the fourth transistor MN2.

Abstract: A barrier layer (20, 62) for an integrated circuit structure is disclosed. The barrier layer (20, 62) is a refractory metal silicon compound, such as a refractor metal silicon nitride compound, formed in an amorphous state. The barrier layer (20, 62) has a relatively low composition ratio of silicon, and of nitrogen if present, to provide low resistivity in combination with the high diffusion barrier properties provided by the amorphous state of the film. A disclosed example of the barrier layer (20, 62) is a compound of tantalum, silicon, and nitrogen, formed by controlled co-sputtering of tantalum and silicon in a gas atmosphere including nitrogen and argon. The barrier layer (20) may be used to underlie copper metallization (22), or the barrier layer (62) may be part or all of a lower plate in a ferroelectric memory capacitor (70).

Abstract: Unique methods and apparatus for maintaining timing in spread spectrum communications are described. One method involves the steps of repeatedly incrementing an N-bit master binary counter at a chip rate to provide a count that rolls over at or near the end of a nominal zero-offset pseudorandom noise (PN) sequence having a length of 2N. The method includes the further steps of, for each counter of a plurality of N-bit slave binary counters, repeatedly incrementing an N-bit slave binary counter at the chip rate to generate a count that is out-of-phase with the count associated with the N-bit master binary counter by a base station offset value and a path delay value.