Abstract: The present invention relates to a source driver circuit (200) for driving a thin film transistor liquid crystal display (TFT-LCD) panel. The source driver circuit (200) provides several different operating modes for the driver to lower the power consumption of a TFT-LCD module while still providing a wide analog voltage range to the liquid crystal display elements. A mode signal (MODE) switches the driver from gray scale to standby mode wherein the internal resistive digital to analog converter (202), decoder/output voltage drivers (210) and output buffer amplifiers (212) are powered down. In addition, only the most significant bit of data corresponding to red, green and blue are transferred to a sample and hold register (206, 208). Output cells (216), substituting for the decoder/output voltage drivers, receive one-bit data from hold registers (208) and provide voltage at the output of the driver circuit (200).

Abstract: A digital sample rate converter converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal Dout having a second sample rate (Fs_out), wherein an upsampling circuit (3) upsamples the digital input signal (Din) by a factor of N and a feedback algorithm circuit (23A) receives a corresponding digital signal of the same sample rate (Fs_in*N) to produce a digital signal (X6) having a sample rate which is a second predetermined factor (M) times the second sample rate (Fs_out). That signal is filtered by a decimation filter (17) and then downsampled by a predetermined factor to produce the digital output signal (Dout) with the second sample rate (Fs_out).

Abstract: A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Abstract: A bi-cosine filter having a scaling technique to process images for up-scaling that does not lead to loss of the high frequency content of the generated image nor leads to image artifact known as waxing and waning is disclosed. The two tap filter (100) includes an input node (102) coupled to receive the image data. A first multiplier (104) couples to receive a first coefficient (C0) and the image data input. The first multiplier (104) multiplies the image data input by the first coefficient (C0) to provide a first product. The image data input is feed through a delay element (106) to delay the image data by a predetermined time period. Delay element (106) connects to a second multiplier (108) that couples to receive a second coefficient (C1). The second multiplier (108) multiplies the time-delayed image data by the second coefficient (C1) to provide a second product.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand (600) and a second 32-bit operand (602) are treated as four 16-bit fields and the sixteen bits in each field are saturated separately. Multi-field saturation circuitry is operable to treat a source operand as a number of fields, such that a multi-field saturated (610) result is produced that includes a number of saturated results each corresponding to each field. One instruction is provided which treats an operand pair as having two packed fields, and another instruction is provided that treats the operand pair has having four packed fields. Saturation circuitry is operable to selectively treat a field as either a signed value or an unsigned value.

Abstract: An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.

Abstract: A method for performing error correction code operations on data to be read from the disk (12) of a hard disk drive (10) includes applying a first error correction code algorithm to a first set of data to be written to the hard disk drive, and a second error correction code algorithm, different from the first, to a second set of data to be written to the hard disk drive (10). The first and second error correction code algorithms may for example produce a different number of error correction code bits for application to said data. The selection between the first and second algorithms may be made, for instance, in dependence upon the physical locations (76, 78) on the disk, or in dependence upon the type of said data (80) to be written. By reducing the number of ECC bits that need be associated with at least some of the data to be written to the disk (12), the available space on the disk for user data can be increased.

Abstract: This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

Abstract: A system that permits use of existing cable TV wiring for home networking is disclosed. Because of the presence of splitters, notch filters, and other components in the cable distribution system, certain of the premises installations in the system can locally communicate over the same frequency as one another, without interference. In a disclosed embodiment, the cable operator determines the attenuation and isolation among different premises in the system, and then assigns home network frequencies to the particular premises, with those premises installations that are sufficiently isolated from one another being assigned the same home network frequency.

Abstract: An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer fabrication and packaging technology. The device is contained within a hermetic cavity produced by bonding a silicon wafer with active circuits to an etched silicon wafer having cavities which surround each device, and bonding the two wafer by either thin film glass seal or by solder seal. The etched wafer and thin film sealing allow conductors to be kept to a minimum length and matched for improved electrical control of the circuit. Further, the device has capability for a ground ring in the solder sealed device. The devices may be packaged in plastic packages with wire bond technology or may be solder connected to an area array solder connected package.

Abstract: A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: A port fitting (102) is formed with a closed, pedestal end forming a diaphragm (102a) on which a strain gauge sensor is mounted. A support member (106) is received on the pedestal end and is formed with a flat end wall (106a) having an aperture (106d) aligned with the sensor. A circuit assembly (108) is bonded to the flat end wall and the sensor wire bonded to the electronic circuit. A cover member (114) placed on the support member, is provided with a cavity for a metal shield member (118) fitted inside the cover member before assembly. The shield member is formed with spring members (118b) extending outside the perimeter of the cover member. The cover member is formed with circular cavities (114d) extending in an axial direction to provide seating for contact spring members (117), making electronic contact to the sensor electronics and protruding beyond the body of the cover member. The cover member is also fitted with a circular elastomer gasket member (116), providing an environmental seal.

Abstract: Micro-electromechanical apparatus and method with position sensor compensation to compensate for sensor drift. A preferred embodiment comprises modifying the intensity of a light source used in position detection to maintain a constant sum of the voltages output from photodetectors receiving light from the light source. Preferred embodiments may be implemented in digital signal processor code, or external to the processor in analog circuitry. By adjusting light source intensity, position calculations may be performed without normalization, and thus without a time-consuming division operation.

Abstract: Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a gate structure over the semiconductor substrate, wherein a dopant material is implanted at an angle around the gate structure to form a halo structure in a source/drain region of the substrate and underlying a portion of the gate structure. A trench is formed in the source/drain region of the semiconductor substrate thereby removing at least a portion of the halo structure in the source/drain region. A silicon material layer is then formed in the trench using an epitaxial deposition.

Abstract: A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.

Abstract: The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide (105) over the deposited copper seed layer (110) by exposure to a substantially copper-free reducing agent solution (120), such that the copper oxide (105) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer (125) over the copper seed layer (110). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.

Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.

Abstract: System and methods are provided for monitoring circuit performance and correcting for variations in current reference signals to maintain a desired Voltage Output Differential (VOD) between the two differential output signals. A voltage signal associated with VOD is compared to a signal that is set to a desired voltage level based on a desired VOD. By determining whether the VOD level is higher or lower than the desired level, adjustments are made to at least one of an output current source level and an output current sink level. An increase in the source and sink currents at the output results in an increased VOD, while a balance decrease in the source and sink currents results in a decreased VOD.