Abstract: The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under blue and green pixels 24 and 22 but not under red pixels 20 in a standard RGB pattern color filter array.

Abstract: The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of the invention, each incoming frame of data is packed and stored in blocks of no more than a predetermined block size, each block have an associated tag of control data and an associated pointer stored in a pointer memory for locating the block of data.

Abstract: A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top metal interconnect layer (118). The protective overcoat (134) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer (136). A sinter that is normally performed after forming the bondpad windows is either omitted or the temperature of the sinter is kept at or below 350° C.

Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.

Abstract: Parameters characterizing physical operation of a rotating structure (disk drive) are determined by sending appropriate commands and examining the response. The measured parameters are then used to balance various requirements. For example, when starting retrieval of a data stream, a speed which leads to highest effective retrieval rate may be used such that the data elements are available quickly for use. On the other hand, in a playback mode (or a shock mode), a speed which consumes the lowest amount of electrical energy can be used.

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.

Abstract: A method for removing sacrificial layers during the process of fabricating micro-mechanical devices with a solution of super-critical carbon dioxide. A mixture of super-critical carbon dioxide with other solvents, co-solvents and surfactants is used during the process to remove sacrificial layers. The disclosed method has many advantages over the prior art, including a reduction of capillary forces that can damage the free-standing micro-mechanical superstructures, an absence of plasma induced damage caused by ashing operations, and a reduction in the use of environmentally sensitive chemicals. Another advantage of the disclosed process is that the swelling of the photoresist layers is minimized. The disclosed method may be used to remove sacrificial layers that were deposited during the process of fabricating micro-mechanical devices. The method is also effective to remove a protective recoat layer that is deposited over a micro-mechanical device after it has been fabricated.

Abstract: A combined pressure responsive electrical switch and temperature sensor device (10, 10′) is shown comprising a base member (12) mounting an electrical switch actuatable by a pressure responsive snap-acting disc (16) attached to a port fitting (22) having an elongated temperature sensing portion (22h, 22h′) extending from the fitting within a threaded bore of the fitting adapted to be inserted in the bore of a fluid pressure source nipple (2). A thermistor (24) is disposed at the distal end (22k, 22k′) of the temperature sensing portion and is electrically connected to terminals (14) of the base member.

Abstract: A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation lookaside buffer (TLB) (300, 310(n)) of a memory management unit (MMU) and thereby access memory and devices. These resources can be instruction processors, coprocessors, DMA devices, etc. Each entry location in the TLB is filled during the normal course of action by a set of translated address entries (308, 309) along with qualifier fields (301, 302, 303) that are incorporated with each entry. Operations can be performed on the TLB that are qualified by the various qualifier fields. A command (360) is sent by an MMU manager to the control circuitry of the TLB (320) during the course of operation. Commands are sent as needed to flush (invalidate), lock or unlock selected entries within the TLB. Each entry in the TLB is accessed (362, 368) and the qualifier field specified by the operation command is evaluated (364).

Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide and/or cap oxide from the PMOS gate areas before doing PMOS implanting steps(K and M). The capping of the wafer (step G)with the cap oxide after the NMOS implant also prevents the arsenic from out diffusing from the silicon. Further embodiments include implanting directly on the base.

Abstract: A new method for phase locking the color wheel in a color field-sequential projection display. At periodic interrupts, the method determines which color wheel index mark should be driven into coincidence with the Vsync signal. It does this by measuring the delay between Vsync and any index mark and then based on the current state of the spoke-sync counter and this delay value, a new next state is determined to drive the nearest index mark to Vsync to the Vsync position. At worst case this technique requires only one-half a color wheel revolution of phase correction to re-lock the system when the TV channel is changed and for the 5/2 and 7/2 spoke-sync modes, popular 50 Hz and 60 Hz modes, only one-quarter revolution of phase correction of the color wheel is required for re-lock.

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Accesses to the cache are qualified by comparing (1244) a task ID and resource ID proffered with a cache request to values stored in the tag entry.

Abstract: A method for generating image compression quantization matrices is disclosed. A method includes a step of locating a frequency coefficient (120) within a transform array (107). A method also includes a step determining a frequency content (122) for the frequency coefficient (120). Method also includes the step of determining the orientation content for the frequency coefficient (120). The method also includes the step of selecting a quantization matrix (110) correlating to the frequency content (122) and the orientation content. The method also includes the step of quantizing the transform array (107) with the quantization matrix (110).

Abstract: The invention relates to a reference voltage source including a bipolar transistor having a base, a collector and an emitter electrode. The reference voltage source further comprises a Schottky diode (D) whose anode is connected to the base electrode of the bipolar transistor and whose cathode is connected to the collector electrode of the bipolar transistor. The currents flowing through the Schottky diode and bipolar transistor are each set so that a temperature-independent reference voltage (VREF) materializes at the collector electrode of the bipolar transistor.

Abstract: A graphical solutions development system using placement of blocks representing hardware/software functionality on a computer screen drawing and connecting the blocks by wires representing data and control flow to create application programs and/or hardware design. The blocks are instances of development components that include intelligence for optimization within a detected environment. This permits effective programming of digital signal processors and system design by users not expert in digital signal processing programming and system design.

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a semiconductor device to have a dimension greater than a critical dimension of a gate to be formed. The polysilicon layer overlies a substrate layer. The method also includes incompletely etching the polysilicon layer. The method also includes forming a source region and a drain region in the substrate layer through the incompletely etched polysilicon layer by doping the substrate layer and applying heat at a first temperature. The method also includes forming a source extension and a drain extension in the substrate layer after forming the source region and the drain region by doping the substrate layer and applying heat at a second temperature.

Abstract: An improved touch screen controller including a comparator and an analog-to-digital converter. The comparator of the touch screen controller detects a touch of the touch screen while the analog-to-digital converter is powered down. The Data Out (DOUT) line of the touch screen controller is used to signal the microprocessor that a touch has occurred. The unique structure of the improved touch screen controller and the fast switching edges of the comparator output signal provide for a faster touch screen controller that consumes little power without requiring a dedicated pin for the touch signal.