Abstract: A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile map is generated (1104) to indicate active tiles. An active tile is selected (1106) and the portion of the buffer corresponding to the active tile is transferred (1108) from a first memory, typically an off-chip memory, to a second memory, typically an on-chip memory to allow a processor to render the band buffer tile. The portion of the band buffer is rendered (1110) and returned (1112) to the first memory. The next active tile is selected and the process continues until all active tiles have been rendered (1114).

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

Abstract: A wireless LAN monitoring application runs on a computing device and scans through all possible wireless channels. The application then displays information indicative of the communication activity level on each channel and permits a user to select a channel having an access point with which to associate. The selection may be based on a desired network the user wishes to access, a channel that has the highest signal-to-ratio, signal quality, or channel utilization or, when looking for a channel to set up an ad hoc network, a channel that has a low signal-to-noise ratio, signal quality, or channel utilization.

Abstract: A non-robust test pattern, which causes a transition on a path of interest as well as off-paths, may be selected as being suitable for performing delay analysis of the path of interest (e.g., critical path) if the transitions caused on the off-paths would not overlap with the transition caused on the path of interest. In other words, an aspect of the present invention enables at least some non-robust test patterns to be used for performing delay analysis. As non-robust test patterns (as well as robust test patterns) can be used to perform delay analysis, the number of possible test patterns for performing speed analysis can be increased.

Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.

Abstract: The specification discloses a system and related method for retrieving encoded media content, such as retrieving audio tracks from a CD in MP3 format. The system involves attaching indicia to the media, or possibly a case or protective cover of the media, which uniquely identifies the content. An encoding retrieval and playback device has the ability to obtain the unique number identified by the indicia, where obtaining the unique number may be a consumer entering the number, may be by reading a barcode label, may be by reading the number from a radio frequency device and the like. Once the unique number has been obtained, the encoding retrieval and playback device retrieves the encoded media content from a server across a network connection. In this manner, a consumer need only be present to initiate the retrieval process, and the retrieval of the encoded media content may be completed without the presence of the consumer, and without inserting the storage media in the playback device.

Abstract: The firmware may contain multiple application modules, which can operate independent of each other such that upgrade of one application module does not affect the operation of the other. A backup copy of a module is stored in a non-volatile memory before upgrading the module from a previous version to a newer version. If the upgrading operation fails, the backup copy is used to restore the previous version. To simplify the upgrading or restoring operations, each application module may be assigned to a pre-specified area of a non-volatile memory forming a firmware. As a result, upgrading or restoring may merely require replacing of a version in the firmware.

Abstract: A central office modem (50) that includes the capability of single-ended loop testing (SELT) is disclosed. The modem (50) includes a digital signal processor (54), a codec (56), line driver and receiver circuitry (58), and a hybrid circuit (60), by way of which a subscriber loop (LOOP) can be driven and sensed. The line driver and receiver circuitry (58) may include a transformer (74a, 74b) for driving the loop (LOOP), or the output may be capacitively coupled. The line driver and receiver circuitry (58) includes active termination, by way of operational amplifiers (80a, 80b). Switches (82a, 82b; 84a, 84b) are provided to selectively enable and disable the active termination function, and to selectively bypass or include the hybrid circuit (60). This control of the line driver and receiver circuitry (58) provides the ability to calibrate out its own characteristics, providing high precision SELT measurements of the load impedance type, and of frequency domain reflectometry, and time domain reflectometry.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: The present invention provides, in one embodiment, a method of making thin uniform ternary diffusion barrier layers 150. The method includes introducing first 105, second 135, and third 145 deposition gases one at a time into a chamber 110 to form a conformal ternary layer 150 within an opening 120 located in a dielectric layer 130. Such ternary diffusion barrier layers 150 may be advantageously used in integrated circuit fabrication.

Abstract: A wireless network, including a plurality of network elements such as a wireless access point (9), and computer stations (2, 4, 6), is disclosed. The wireless network operates so that each network element (2, 4, 6, 9) waits for a pseudo-randomly selected duration, after the end of a frame on the channel, before initiating transmission. One of the network elements, such as the wireless access point (9), measures the performance of the network over a measurement period (T), and adjusts a minimum value of the upper limit of the range from which the random duration is selected, according to the performance of the network over the measurement period. The times measured may be the successful transmission time (Ts), which is maximized in adjusting the minimum value, or the idle and collision times (T1,Tc), which are equated in the optimization of the minimum value.

Abstract: A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.

Abstract: A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the compensation capacitors 50 and 52 conventionally coupled to internal high impedance gain nodes 40 and 42, but has the other plates of the compensation capacitors 50 and 52 unconventionally driven with the input signal IN+ and IN−. The voltages appearing across the compensation capacitors 50 and 52 in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plates of the compensation capacitors are coupled to ground. Since little current is now required to charge the compensation capacitors 50 and 52, the input stage tail current no longer limits the slew rate.

Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.

Abstract: A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located in the path of the projected radiation. The cartridge (26) includes a photomask (34,36) located in the path of the projected radiation and a Fabry-Perot interferometer (54) located in the path of the projected radiation. A radiation-sensitive material (30) is located in the path of the projected radiation such that the projected radiation encounters the reticle cartridge (26) before the projected radiation encounters the radiation-sensitive material (30).

Abstract: A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

Abstract: A system and method for correcting spatial banding artifacts in print images. The system includes: a light source, a spatial light modulator, a transport system for transporting a substrate on a carrier allowing the spatial light modulator to form an image on the substrate; a first encoder (26) that attaches to the carrier and senses its movement; a second encoder (36) attached to the drive circuit (34) of the transport system to sense operation of the drive circuit (34); a first circuit (20) that receives the information from the first encoder and adjusts operation of the spatial light modulator; and a second circuit (30) that receives the signal from the second encoder and adjusts operation of the drive circuit to coordinate movement of the substrate and the image to avoid artifacts. The method for establishing this system is also disclosed.

Abstract: A semiconductor testing device having a nest for holding an integrated circuit during testing. The nest comprises a plate having a front side and a back side, a cavity in the plate for receiving an integrated circuit having a plurality of pins, a channel for receiving therein an anvil, and an anvil detachably engaged within the channel, positioned to engage the pins of the integrated circuit and to maintain the pins in alignment.