Patents Assigned to Texas Instruments
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Patent number: 6734721Abstract: A method for affecting speed of transition of a closed loop circuit from an initial state to a steady state during a transition period; the closed loop circuit including a switching unit effecting the transition in response to a gating signal applied to a gate locus at a value greater than a predetermined threshold potential; includes the steps of: (a) at least one of: (1) clamping the gate locus at a minimum potential greater than ground potential and less than the predetermined threshold potential; and (2) increasing potential at the gate locus at a plurality of various rates during a plurality of segments of the transition period.Type: GrantFiled: January 27, 2003Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Davy H. Choi
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Patent number: 6735146Abstract: In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.Type: GrantFiled: September 10, 2002Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, David Toops
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Patent number: 6734477Abstract: Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. In a first embodiment, the ferroelectric device level is disposed over an isolation layer of the transistor level and an isolation layer of the ferroelectric level has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith. In a second embodiment, the first metal level and the ferroelectric device level are integrated into the same level. In a third embodiment, the ferroelectric device level is disposed over the first metal level. In a fourth embodiment, the ferroelectric device level is disposed over the inter-level dielectric level that, in turn, is disposed over the first metal level.Type: GrantFiled: August 8, 2001Date of Patent: May 11, 2004Assignees: Agilent Technologies, Inc., Texas Instruments, Inc.Inventors: Ted Moise, Scott Summerfelt, Eden Zielinski, Scott Johnson
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Patent number: 6735724Abstract: A method of monitoring the performance of a Viterbi detector by using the deviations from the noiseless case of the path difference of the two branches entering the minimal state for a number of samples.Type: GrantFiled: April 7, 2000Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Brett A. McClellan
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Patent number: 6734741Abstract: A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word.Type: GrantFiled: November 30, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Dirk Leipold, Khurram Muhammad, Chih-Ming Hung
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Patent number: 6735260Abstract: An adaptive data slicer which functions to adapt to changes in the properties of a signal input thereto by producing a near optimal slicing threshold in accordance with the input signal for use in a decision circuit. The slicing level is considered optimal when its use in the decision circuit minimizes the bit error probability. The data slicer utilizes two peak detectors, a maximum peak detector for detecting the highest levels of the input signal and a minimum peak detector for detecting the lowest levels of the input signal.Type: GrantFiled: April 17, 2000Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Oren Eliezer, Yaron Kaufmann, Yasuhiro Satoh
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Patent number: 6735034Abstract: A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.Type: GrantFiled: June 22, 2000Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Ashish Manjrekar, Echere Iroaga, Bryan Bloodworth, Paul Merle Emerson
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Patent number: 6734738Abstract: A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to the frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency.Type: GrantFiled: March 25, 2002Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Kouzou Ichimaru
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Patent number: 6734068Abstract: An embodiment of the instant invention is a method of forming a semiconductor device situated over a semiconductor substrate, the method comprising the steps of: forming a layer of suboxide material (layer 206 of FIG. 2a) over the substrate (substrate 202 of FIGS. 2a-2c), the suboxide material comprised of a material selected from the group consisting of: HfSiOx, ZrSiOx, LaSiOx, YSiOx, ScSiOx, and CeSiOx; and forming a structure (layer 210 of FIG. 2c) on the layer of suboxide material. In an alternative embodiment, semiconductor device is a transistor where and the structure formed on the layer of suboxide material is a gate electrode (preferably comprised of: polycrystalline silicon, tungsten, titanium, tungsten nitride, titanium nitride, platinum, aluminum, and any combination thereof.Type: GrantFiled: May 9, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Glen D. Wilk
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Patent number: 6733683Abstract: A method of manufacturing an array of microstructures, such as a micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network system, is disclosed. The micromirror array assembly (10, 20) includes a plurality of mirrors (29) monolithically formed from a silicon wafer (70) with a frame (43), attached by way of hinges (55) and gimbal portions (45). The wafer is temporarily bonded to a support wafer (60) while permanent magnets (53) are attached to each of the gimbal portions (45) associated with the mirrors (29), through holes etched through the mounting wafer (60). The resulting frame (43) is then mounted to a coil driver assembly (50) so that coil drivers (34) can control the rotation of each mirror (29), under separate control from control circuitry (14, 24). The micromirror array assembly (10, 20) is able to support higher signal energy at larger spot sizes, and also enables multiplexed transmission and receipt, as well as sampling of the received beam for quality sensing.Type: GrantFiled: August 29, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Andrew S. Dewa
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Patent number: 6735030Abstract: A write drive circuit (40) for a hard disk drive selectively providing a current mode operation for high speed data write of a single channel, and selectively providing a voltage mode operation during a servo write operation. A central buffer has a first circuit (50) providing a current mode drive signal to a head during a single channel write operation, and a second circuit (52) providing a voltage mode drive signal for multi-channel servo write operation. The outputs of both circuits (50, 52) is provided over a common differential connection (T1) feeding a pre-driver circuit (70) adapted to drive one or many heads, as determined by head select control lines (72). The circuit provides >1.6 Gb/s data write speed in single channel write operation, and has an architecture utilizing only two signal lines for four channels.Type: GrantFiled: October 29, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Tuan Van Ngo, Raymond Elijah Barnett, Scott Gary Sorenson
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Patent number: 6735652Abstract: A circuit determining whether a present value transmitted on a bus equals any of several desired values. The circuit may contain a monitor random access memory (RAM) and a monitor circuit. The bits of a desired value at a second set of positions are stored in a location (of the monitor RAM) having an address formed by the bits of the desired value at the a first set of positions. When a value (“present value”) is transmitted on the bus, the bits of the present value at the first set of positions are provided as an address to the monitor RAM, which generates the bits stored in the addressed location as output. The monitor circuit compares the output of monitor RAM with the bits of the present value at the second set of positions to generate a result. The result indicates if the a desired value has occurred on the bus.Type: GrantFiled: May 3, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Venkatesh Natarajan, Rajendra S. Marulkar
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Patent number: 6734705Abstract: The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.Type: GrantFiled: August 12, 2002Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Mark Pulkin, David D. Briggs
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Patent number: 6735737Abstract: A parallel Chien search by partitioning of the nonzero elements of a root field and using a parallel Galois multiplier.Type: GrantFiled: February 20, 2001Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Jagadeesh Sankaran, David Hoyle
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Patent number: 6734711Abstract: An input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition stabilizer circuit includes a resistor having a first terminal connected to the input of the input circuit;, and a capacitor. A first MOS device is connected by a source and a drain between a second terminal of the resistor and a first terminal of the capacitor, while a second MOS device is connected by a source and a drain between a second terminal of the capacitor and ground. A delay circuit is adapted to provide a signal to a gate of the first MOS device and a gate of the second MOS device corresponding to a signal at the input of the input circuit, but delayed by a first predetermined interval. In some embodiments the delay circuit is provided in two parts, with the signal provided to the first MOS device being delayed by a further amount, as compared with the signal provided to the second MOS device.Type: GrantFiled: April 1, 2003Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Eugene B. Hinterscher
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Patent number: 6734521Abstract: According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a first logic path. The first transistor has a first contact, a first gate length and a first contact to gate centerline spacing. The method also includes providing a second transistor in a second logic path. The second transistor has a second contact, a second gate length and a second contact to gate centerline spacing. The first contact to gate centerline spacing is substantially equal to the second contact to gate centerline spacing. The method also includes selecting a different gate length for the first gate length using a predetermined design criterion.Type: GrantFiled: August 30, 2002Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventor: Theodore W. Houston
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Publication number: 20040088524Abstract: A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instruction. If there are less than a threshold number of consecutive supported instructions before the next unsupported instruction, the second processor loads the instructions in the first processor for execution so that the first processor does not fetch the instructions. If there are more than a threshold number of consecutive supported instructions before the next unsupported instruction, the first processor fetches and executes those instructions.Type: ApplicationFiled: July 31, 2003Publication date: May 6, 2004Applicant: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre
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Publication number: 20040084059Abstract: A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment of the present invention, a cleaning chemistry comprising nitric acid, hydrofluoric acid, and phosphoric acid in solution with deionized water is applied to the wafer surface to be cleaned preferably while subjected to megasonic assist cleaning. The wafer is preferably then subjected to brush scrubbing and a deionized water rinse with megasonic assist cleaning.Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Applicant: Texas Instruments IncorporatedInventors: Changfeng Xia, Linlin Chen
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Publication number: 20040085121Abstract: A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one or more logic elements within the integrated circuit are set to one or more selected values. The selected values produce a minimum leakage current associated with the integrated circuit when the integrated circuit is operating in a standby mode.Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Applicant: Texas Instruments IncorporatedInventors: Clive D. Bittlestone, Vipul K. Singhal
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Patent number: 6730597Abstract: A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based solution to remove surface contamination (122) and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).Type: GrantFiled: September 21, 2000Date of Patent: May 4, 2004Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Linlin Chen, David Gonzalez, Jr., Honglin Guo