Abstract: The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between a storage node (230) and a bitline (200). The NMOS transistor is gated by the wordline (190). A PMOS drive transistor (180) is connected between the storage node (230) and a supply voltage (255).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A home networking transmitter (100), receiver (200), station (300), network manager (404), network (400) and method adapted to network devices (344/336/338/346) over phone lines (406) in a home. A bandwidth other than the 4 to 10 MHz band defined in the HomePNA 2.0× specification and a Baud rate higher than 4M baud may be used for communications between a plurality of devices (334/336/338/346). PHY and MAC layers are improved to increase the performance of home phone line networks. Advantages in the PHY layer include numerous higher symbol rates, higher constellations, variable power level, error correcting codes, byte interleaving, ISI-free pulse shape and pre-equalization. Advantages in the MAC layer include managed bandwidth resources allocation, guaranteed quality of service for latency sensitive applications, solicited grants, support to devices with low power consumption and support to device with low processing power.

Abstract: A receiver system (10) includes a first stage of modulation (46, 51) which modulates a radio-frequency input signal (17), and a second stage of modulation (56, 61, 66, 71) which modulates outputs from the first stage. Combining circuits (76, 77) combine selected outputs of the second stage to produce two outputs (18, 19) from the receiver system. The first stage receives modulating signals (22, 23) from a first oscillator (21), and the second stage receives modulating signals (27, 28, 32, 33) from second and third oscillators (26, 31). The second and third oscillators each operate at a substantially lower frequency than the first oscillator. The phase difference between the modulating signals produced by each of the second and third oscillators is adjusted so that there is minimum image power in each of the system outputs (18, 19), even if the modulating signals from the first oscillator are not in phase quadrature.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time needed for such screening by discriminating when screening is not needed. In a first embodiment, the rendering process produces a minimally enclosing bounding box surrounding all rendered objects. In an alternative embodiment, scan lines including any part of a rendered object are noted. The screening makes better use of memory by dividing each row of a preference matrix into segments. The lookup tables associated with these segments are sequentially loaded into a memory cache. Input pixels mapping into the loaded segment lookup tables are screened. Then the lookup table associated with the next segment of the preference matrix are loaded into the memory cache and used to screen input pixels mapping into that segment.

Abstract: An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor devices formed in regions of the substrate 10 having different characteristics. Transistors 50 and 52 can be formed on the same substrate 10 and have different electrical characteristics.

Abstract: A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type that is complementary to the first conductivity type. The method includes the steps of forming a first gate stack (100), the first transistor including the first gate stack and forming a second gate stack (80), the second transistor including the second gate stack. The method further includes implanting a first drain extension region (107) at a first distance relative to the first gate stack, the first transistor including the first drain extension region, and the method includes implanting a second drain extension region (87) at a second distance relative to the second gate stack, the second transistor including the second drain extension region. The first distance is greater than the second distance.

Abstract: A programmable line terminator device that can optimally terminate a transmission line or bus even if the line impedance is variable or not well defined. The line terminator includes a programmable multi-line active terminator for terminating the bus. The line terminator provides programmable termination impedance and bias for a plurality of lines on the bus. The line terminator may be uniquely addressed and programmed via address and control signals carried by one or more of the lines on the bus. The line terminator detects what type of bus it is terminating and what types of devices are connected to the bus. The line terminator includes a mechanism for adjusting the termination impedance and bias for the lines on the bus based on the bus type, the types of devices connected to the bus, and/or the control signals carried by the bus or one or more lines separate from the bus.

Abstract: A processor, comprising a monitor for measuring the relative amount of idle time within the processor, results of the measuring being used by the processor, depending upon the respective embodiment, to modify processor clock speed in response to a utilization percentage of the processor being below a preselected level, or to modify a clock speed of the processor to control a utilization percentage of the processor. Another embodiment discloses a processor, comprising a monitor for measuring the relative amount of idle time within the processor, results of the measuring being used by the processor for providing a signal for circuitry for controlling periods of time a processor clock is in an OFF state, the length of the periods of time said clock is in an OFF state being appropriate to allow the processor to operate at an efficient utilization percentage.

Abstract: A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and materials while resulting in uniform and proper device structuring, is disclosed, providing a system using a reactive plasma to selectively form diffusion barriers and provide selective oxidation.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125) and an optional patterned silicon oxide layer (135) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (170) during the formation of metal silicide regions (160) on the integrated circuit resistor (170).

Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

Abstract: A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

Abstract: Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The ferroelectric capacitor residing over the first and second circuit elements, and first and second contacts, has a conductive plate that may be used as a local interconnect layer. The conductive plate extends between and electrically couples first and second circuit elements directly through first and second contacts of the ferroelectric memory device. Methods are also provided for forming the local interconnect layer within the conductive plate of the ferroelectric capacitor.