Abstract: According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: The present invention provides a low drop-out voltage regulator (200) that reduces gate capacitance and simplifies the compensation needed to maintain stability, without requiring additional and/or larger Miller capacitors (108), by splitting the output (220, 221) of the driver (112A) for different operational modes, selectively driving a small power device (206), a large power device (214) or both based on the mode.

Abstract: A stop band second order active RC filter architecture that does not use a non-inverting input to receive an input signal, and that employs both positive and negative feedback to provide an RC transfer function having an imaginary zero.

Abstract: A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing a memory array column (30) including a plurality of memory cells (10). Each memory cell (10) includes drive transistors (12). A current limiting transistor (34) is coupled to the drive transistors (12). A mode signal (38) is coupled to the current limiting transistor (34). The mode signal (38) is operable to deactivate the current limiting transistor (34). The current limiting transistor (34) is deactivated when the mode signal (38) indicates that the memory array column (30) is in a standby mode.

Abstract: A method of forming an electrical contact is provided. The method includes forming a gate dielectric layer adjacent a body region of a transistor structure and forming a layer of dielectric material at least partially defining a trench adjacent the body region. The method further includes forming a conductive layer extending into the trench. The method further includes removing a region of the portion of the conductive layer extending into the trench to expose a region of the gate dielectric layer. The method further includes removing the exposed region of the gate dielectric layer to expose a contact portion of the body region. The method further includes filling the trench with a gate material such that a contact portion of the gate material is in direct contact with the contact portion of the body region.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also includes depositing a first conducting material within the trench to form a continuous liner layer within the trench. The liner layer is formed at a first predetermined temperature. The method further includes filling a remaining portion of the trench over the liner layer with a second conducting material at a second predetermined temperature. The second predetermined temperature is greater than the first predetermined temperature.

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit. Validity circuitry is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry is connected to the memory circuit and is operable to transfer a block of data to a selected portion of segments of the memory circuit such that a transfer to any segment within the selected portion of segments holding valid data is inhibited. A block transfer to a selected plurality of segments in the memory circuit is initiated (1600, 1624). During the block transfer, each segment is tested (1602) to detect if a segment within the selected plurality of segments holds valid data. A transfer within the block transfer to a segment is inhibited if the segment contains a valid data value (1604).

Abstract: An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit includes a uni-directional switch on the input and one or more bi-directional switches on one or more outputs. Current can flow from the system power supply to any connected peripherals via the uni-directional switch and bi-directional switches, or can flow from the peripheral having the highest voltage power supply to the other peripherals via the bi-directional switches, but current will not flow back to the main system because of the unidirectional switch connected to the system power supply. Over-current conditions are quickly detected and the bi-directional switch is opened to prevent damage or over-heating. The switches are preferably fabricated as power FETs using NMOS technology. Several integrated circuits can be cascaded together to accommodate multiple peripherals.

Abstract: An image information encoding system that includes detecting an image portion for which higher image quality is desired based on the motion vector value and the image error value, calculating a bit rate control value based on the detection result as well as the buffer usage rate, and changing the roughness of the quantization step based on the bit rate control value. The objective is to minimize the degradation of an image due to compression of a still image portion.

Abstract: An embodiment of the instant invention is a method of implementing a vanishingly small integrated circuit diode comprising the steps of: forming an area of a thin dielectric film (201 of FIG. 2) over a conductive silicon surface ( 10 of FIG. 2) of one conductivity type in a region of a thick dielectric film (100 of FIG. 2) over the conductive silicon surface; forming a first conductive path from the conductive silicon surface to an operating circuit; forming a conductive silicon film (202 of FIG. 2) of a second conductivity type over the thin dielectric region; forming a second conductive path from the conductive silicon film to the operating circuit; and causing at least one region of the second conductivity type in the conductive silicon surface and at least one third conductive path through the thin dielectric film wherein said causing consists of applying a voltage or applying a current.

Abstract: As the number of signaling wires increase in integrated circuits, power consumption, related to charging and discharging of wiring capacitance also increases and emerges as a serious obstacle to the advancement of semiconductor technology. The present invention provides a novel quad-state memory element which can be used as a fundamental building block for designing high speed, high density, and low power integrated circuits.

Abstract: A DC-DC switching regulator, adapted to receive a pulsed signal. The regulator includes an inductor, and also includes a capacitor having one port connected to ground, and having a second port providing an output voltage of the DC-DC regulator. A driver is coupled to the inductor and adapted to drive pulses of current to the inductor when the pulsed signal is asserted. A rectifier is adapted to provide a path for the inductor to drive current to charge the first capacitor when the pulsed signal is not asserted. An overcurrent circuit is provided, adapted to sense a threshold current of the switching regulator corresponding to an overcurrent condition and to provide an overcurrent indication signal in response thereto. The overcurrent circuit includes a ringing compensation circuit adapted to control the overcurrent circuit threshold for providing the overcurrent indication signal from a first level to a subsequent second level less than the first level.

Abstract: An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, 60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (yn−1, yn−2), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (xn) and signal output (yn). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

Abstract: A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed using BTBAS processes.

Abstract: A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the step height changes. The resistance of the polysilicon structure is measured by applying a voltage and measuring the resulting current.

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.

Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.