Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.

Abstract: A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction register and at least one data register for supporting testing and emulating a memory subsystem with different types of physical memory in a microprocessor based system.

Abstract: A hard disk drive (HDD) circuit (10) having feedback provided to an input of an differential amplifier setting the amplifier input impedance close to a flexible printed circuit (FPC) characteristic impedance. A matched source and input impedance produces a generally flat gain frequency response. As the result of flat response and wider gain bandwidth, white noise without high frequency peaking can be obtained. Feedback resistors (R5) provide feedback according to the present invention which is superior in terms of the input referred noise since the feedback attenuates both the input signal from the sensor and the noise from the amplifier. Feedback resistors (R5) may be connected through AC coupling capacitors to compensate the voltage differences between amplifier input and output. The circuit of the present invention provides a method to connect the feedback resistors directly from amplifier outputs to inputs which have a different potential.

Abstract: Trimming methods and apparatus are disclosed for selectively removing resistance between first and second nodes in an electrical device, including trim circuits comprising a resistor and a diode formed in the resistor body having a conductive portion which may be selectively melted to short the resistor. A multi-bit trim cell is disclosed having trim cells individually comprising a resistor with a diode formed in the resistor body for selectively shorting the resistor, and a fuse for selectively disconnecting the diode from a trim pad.

Abstract: Sigma delta modulators and digital to analog converters therefor are disclosed, in which intentional mismatch is provided in circuit elements of the digital to analog converter to facilitate tone reduction where dynamic element matching is used in selecting the digital to analog converter circuit elements. Methods are disclosed for fabricating digital to analog converters for providing analog feedback using a group of circuit elements selected according to a quantized output signal in a sigma delta modulator, in which a plurality of matched circuit elements having values within a tolerance amount of a design value are provided in the group along with at least one mismatched circuit element having a mismatched element value differing from the design value by a mismatch amount, where the mismatch amount is greater than the tolerance amount.

Abstract: The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

Abstract: A direct comparison adaptive halting turbo decoder computes the sum of the a priori and the extrinsic information sequences at each iteration step. The sum sequences are coded so as to be simple binary sequences. New sum sequences are generated during each iteration and used to estimate the state of the convergence without resorting to use of transmitted error detection codes. The adaptive halting turbo decoder is halted when the sum sequences generated in a single iteration step produce identical binary sequences, i.e. a change in the sum sequence is observed during the iteration and when there is no more change, the iteration is halted.

Abstract: According to a broad aspect of the invention, a method and apparatus are presented for identifying a track (42) of a rotating disk (12) of a mass data storage device (10), using EPR4 data detection techniques. The track identification indicia (64) may be written more densely than the track identification indicia would have been written without using EPR4 data equalization techniques, wherein track identification indicia pulses (110-113) may at least partially overlap. The identification indicia (110-113) is read from the disk (12) using a read head (18), and processed using EPR4 data equalization techniques in an EPR4 Viterbi detector (92). The Viterbi detector (92) may be used also to detect data pulses (64) by switching its mode of operation from a track identification mode to a data detection mode.

Abstract: A hermetic motor protector (10) has a non-current carrying snap-acting thermostatic disc (26) freely disposed on a disc seat (22a) having a tab (22c) projecting through a centrally located aperture (26a) in the disc. An outer peripheral portion of the disc is received under a leg (22e) of the bracket limiting upward motion of the disc at that location and causing the disc to act as a lever pivoting about the disc seat (22a) as a fulcrum so that the outer peripheral portion of the disc diametrically opposite to leg (22e) engages a motion transfer bump (28d) formed on a movable contact arm cantilever mounted on leg (22e) when the disc snaps from its normally contacts engaged configuration to its opposite dished contacts open configuration when the disc is heated to its actuation temperature by a heater element (24) along with heat conducted from a motor with which the protector is used.

Abstract: Transponders present in an interrogation zone can be identified by an interrogator by it sending an RF interrogation signal into the interrogation zone, the RF interrogation signal containing a code string prompting the transponders to generate partial addresses. As soon as one transponder “sees” that the generated partial address agrees with part of its own address, it responds by sending its full address which can then be read by the interrogator. Immediately after having received a full address the interrogator sends a code string characterizing the address of the transponder having responded before so that this transponder is thereby addressable. The signal sent by the interrogator to the transponder with this code string also contains an instruction which prompts the transponder to assume the condition in which it no longer responds to receiving its address or partial address.

Abstract: A printer forms an approximate of a Bezier curve as a sequence of line segments. Two parametric equations, X(t) and Y(t), are employed. Two methods can be used to evaluate the parametric equations. Both use fixed point integer arithmetic to directly calculate points along the curve which are the values of the X(t) and Y(t) equations. The first method sets the number of steps of the parametric variable are equal to an integral power of 2. This gives a predictable execution time and uses line segments to connect the points as a piecewise straight line approximation to the curve. The number of steps is set as the next higher power of 2 than an estimated length of the curve. The second method allows Y(t), the scan line variable, to change only in predetermined integer steps. The value of X(t) is evaluated for each t corresponding to the integer step in Y(t). This second method has a natural advantage, if a closed path is being decomposed as a run array rather than a collection of trapezoids.

Abstract: A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal end and is formed with a flat end wall having an aperture aligned with the sensor. A portion of a flexible circuit assembly is bonded to the flat end wall with a connector disposed over the support member. A tubular outer housing is fitted over the several components and its bottom portion is welded to the port fitting while its top portion places a selected load on an O-ring received about the connector as well as internal components of the transducer. In one embodiment, a loading washer (72a) is disposed over the O-ring on a first portion (70a) of a two portion connector (70) and retained by a second connector portion (70b). Protrusions (76a1) formed on the tubular housing (76) pass through cut-outs in the second connector portion to place a load on the loading washer.

Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.

Abstract: A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: A line driver apparatus includes a peak detector operable to receive a data signal and output a first logic signal when the data signal is below a threshold value and output one of a plurality of alternate logic signals when the data signal exceeds the threshold value. The peak detector includes a signal magnitude calculator operable to calculate an amount by which the data signal exceeds the threshold value. The line driver apparatus also includes an amplifier operable to receive a filtered analog data signal and one of a time-delayed first logic signal and one of a time-delayed alternate logic signal, wherein the amplifier operates at a first voltage level upon receiving the time-delayed first logic signal, and the amplifier operates at a voltage level that is increasing toward one of an alternate voltage level upon receiving the time-delayed second logic signal.

Abstract: A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated circuit. One or more transistors within the integrated circuit are initialized such that a steady-state associated with one or more of the transistors is achieved. A capacitance associated with the portion of the integrated circuit is then measured using the measurement circuit. The portion of the integrated circuit is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement.

Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components (14) in the matrix (10) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.

Abstract: In-circuit-emulation of an integrated circuit permits location and identification of optional emulation resources. Each emulation resource is assigned a memory address. The in-circuit-emulation generates a special memory access to memory addresses. If the special memory access corresponds to the address of an emulation resource, the emulation resource responds with an acknowledgement and a corresponding identification number. Nonemulation circuits do not respond to the special memory access. This technique permits manufacture of plural integrated circuits with corresponding sets of emulation resources, where an emulation program can determine the available resources for the particular integrated circuit. The emulation resources preferrably includes a set of emulation resources common to all integrated circuits with predetermined memory addresses and a predetermined identification numbers as well as optional emulation resources.