Abstract: A digital graphic equalizer uses a predetermined number of equalizing bands each having a different center frequency, and the center frequencies span a predetermined audio bandwidth. For each equalizing band a minimum set of filters is provided. The filters have a predetermined linear uniform spacing between the gain of successive filters.

Abstract: The present invention relates to a fuse and a method for forming a fuse over a semiconductor substrate. The fuse comprises forming a first contact member and a second contact member over a respective first region and a second region of a patterned, electrically-conductive silicide layer, wherein the first contact member and the second contact member electrically contact the silicide layer, thereby defining a first interface and a second interface, respectively. A first contact area and a second contact area are associated with the respective first contact member and second contact member, wherein the first contact area is larger than the second contact area, thereby defining a fusible link at the second interface. According to one example, the silicide resides over a patterned polysilicon layer, wherein the patterned polysilicon layer generally tapered, and wherein the first region is wider than the second region.

Abstract: This CMOS imager represents illuminance in the time domain. Once per frame, each pixel outputs a pulse after a time proportional to the illuminance on that pixel. Therefore, the illuminance on that pixel is related to the time difference between its pulse event and global reset of the imager. A counter reports the times of these pulse events in a digital format. Thus no analog to digital converter is necessary. This imager enables easy computation of pixel intensity histograms. Frame data is stored in pixel intensity order using row and column arbiters to produce a pixel address. Because each pixel has its own exposure time, the imager has a wide dynamic range of 120 dB. This imager has low power dissipation and avoids the noise and mismatch problems of prior complicated analog readout circuits.

Abstract: A way to average alignment measurements that obtains the advantage of multiple alignment marks per shot without requiring actual measurement of all alignment marks on all wafers of a batch. All alignment marks on all sampled shots are measured and averaged on the first wafer of a batch. The offset between a single sampled alignment mark and the average total offset for the wafer is characterized and applied when that alignment mark is sampled on succeeding wafers.

Abstract: An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90) is formed in the source extension region 50 and a transistor drain region 92 is formed between two drain alignment structures (74), (76) in the drain extension region (52).

Abstract: An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prevents erroneous operation. After power is input, in a switching control part 110, a flip-flop X23 is reset, a level change of output signals s1-s5 of an input part 100 is detected by a NAND gate X21, and an output signal s9 of the flip-flop X23 is raised. In a switching part 120, when the signal s9 is at low level, output signals s10-s14 are held at high level, and when the signal s9 is at high level, the output signals s1-s5 of the input part 100 are output to an output part 130. Thus, the output signals are held after the power input, and after the input signal rises, the signal transfer function is started, so that the output of incorrect control signals can be prevented, and thereby erroneous operation of a printer can be prevented.

Abstract: A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is substantially blocked from the second transistor area (302). The angled implant forms pocket regions in the first transistor area (304). The same masking layer (214) may then be used to implant source and drain extension regions in both the first and second transistor areas (304, 302).

Abstract: A fully digitally-controlled LC tank oscillator (DCO) uses a bank of more significant binary-weighted and/or less significant equally-weighted capacitors that are switched between only two voltage potentials. The time-averaged value of capacitance of predetermined less significant capacitors is determined by dithering between the two states to achieve a further refinement in the resolution of the resonating frequency.

Abstract: This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time needed for such screening by discriminating when screening is not needed. In a first embodiment, the rendering process produces a minimally enclosing bounding box surrounding all rendered objects. In an alternative embodiment, scan lines including any part of a rendered object are noted. The screening makes better use of memory by dividing each row of a preference matrix into segments. The lookup tables associated with these segments are sequentially loaded into a memory cache. Input pixels mapping into the loaded segment lookup tables are screened. Then the lookup table associated with the next segment of the preference matrix are loaded into the memory cache and used to screen input pixels mapping into that segment.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120, 122 and 128 of FIGS. 1a-1d) comprised of a metal; forming a dielectric layer (layer 130 of FIGS. 1a-1d) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material 136 and 137 of FIG. 1c) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer.

Abstract: In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count.

Abstract: An apparatus for effecting high speed switching of a communication signal between a first component and a second component includes: (a) a switching circuit configured for receiving the signal from the first component that includes a plurality of switch elements responding to the signal to produce an interim signal that is substantially a model of the signal; (b) a follower circuit having an input locus coupled with the switching circuit for receiving the interim signal; the follower circuit has an output locus configured for presenting an output signal that is substantially duplicating the interim signal; and (c) a control circuit coupling the follower circuit with the switching circuit and receives a feedback signal from the follower circuit representative of the output signal; the control circuit responds to the feedback signal to effect operation of the switching circuit to control at least one first parameter relating to the interim signal.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Abstract: Methods are discussed for forming a transistor comprising a source/drain region having both a graded HDD portion and a sharp HDD portion in a semiconductor substrate. The method comprises a dual diffusion process, wherein a gate structure is provided over the semiconductor substrate having an offset spacer associated therewith. A first dopant material is implanted around the gate structure in the source/drain area to form a grade-HDD region in the substrate that is aligned to the offset spacer. A sidewall spacer is formed around the gate structure and covers the offset spacer. A second dopant material is then implanted in the source/drain area to form a source/drain region in the substrate aligned to the sidewall spacer, and the device is thermally processed in a first anneal. The sidewall spacer and the offset spacer are removed from the gate structure.

Abstract: One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.

Abstract: A charge pump circuit is configured for continuous control of the output of the charge pump circuit through continuous use of at least one charge pump capacitor coupled with a servo amplifier. During and between both phases of operation of the charge pump circuit, the output current from the servo amplifier can be set equal to the load current through a continuous path. This servo amplifier configuration facilitates the continuous regulation of the load current, during both phases of operation, as well as in between the phases, and as a result no load current is drawn from the output capacitor, thus requiring no recharge of the output capacitor. In addition, an exemplary charge pump circuit can be configured with level-shifting capabilities, the ability to facilitate the use of lower voltage processes, and the ability to provide a large DC open loop gain and high stability. In addition, an exemplary charge pump circuit can be configured with capabilities for buck/boost operation.

Abstract: An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.

Abstract: An interface (10) for connecting a calculator (12) to a standard television (11), so that the calculator's display can be re-displayed on the television (1). The interface (10) is useful with different calculators having different display formats. Reformatting of the input signal is accomplished by dividing format detection and reformatting tasks between a field programmable gate array (21) and a microprocessor (23).

Abstract: A clock distribution system and method for an integrated circuit includes a power supply line and a plurality of clock distribution elements. The power supply line is operable to provide resistive-capacitive (RC) filtered power. The clock distribution elements are coupled to the power supply line. The clock distribution elements are operable to be powered by the RC filtered power supply to distribute a reference clock signal.