Abstract: A data processing system is provided with a digital signal processor which has an instruction for expanding one bit to form a mask field. In one form of the instruction, a first bit from a two-bit mask in a source operand is replicated and placed in an least significant half word of a destination operand while a second bit from the two-bit mask in the source operand is replicated and placed in a most significant half word of the destination operand. In another form of the instruction, a first bit from a four bit mask in a source operand is replicated and placed in a least significant byte of a destination operand, a second bit from the four-bit mask in the source operand is replicated and placed in a second least significant byte of the destination operand, a third bit from the four-bit mask is replicated and placed in a second most significant byte of the destination operand and a fourth bit form the four-bit mask is replicated and placed in a most significant byte of the destination operand.

Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit (136) coupled between the USB host (12) and the circuitry (32) for providing a capability to the USB host. The USB interface circuit comprises a memory area (106) comprising a code overlay endpoint (1061) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry (150-163) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space.

Abstract: A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

Abstract: A programmable termination circuit (12) selectively providing a termination voltage to a driver or receiver of a high-speed serial link, such as CML I/O's. The programmable termination circuit (12) is adapted for use both at a transmitter front end (10) and at a receiver front-end (20) to selectively terminate the respective circuit to one of multiple available voltage supplies (VDDA, VDDT), such as 1.8 volts and 3.3 volts. The programmable termination circuit is software controllable via a single control signal (TS). A level shifter (14) circuit is provided for coupling the termination control signal (TS) to the programmable termination circuit (12) to level shift the termination control signal to a logic level suitable with large FETs (M1, M2) coupled to and controlling the connection of the voltage supplies.

Abstract: A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the semiconductor. The scribe line area is indicative of a delineation that separates one or more portions of the semiconductor. A capacitance of one or more elements included within the one or more portions of the semiconductor is then measured using the measurement circuit. The method also includes comparing the capacitance measurement of the one or more elements included within the one or more portions of the semiconductor to a reference set of capacitance values such that a parameter associated with a manufacturing process that generated the semiconductor may be checked.

Abstract: A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to generate horizontal line demarkers in the V-blank (vertical blank) region. The demarkers specify the transition from one line to the other. Such a feature is useful in spread spectrum clocking (SSC) based display signals in which HSYNC signals may also not be available to determine the transitions from one line to another in the V-blank region.

Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

Abstract: A socket (1) has a base (2) on which rows of contact pins 4 are arranged, the contact pins being elastically deformable in the vertical direction, an adaptor (5) having rows of contact holes (5d) arranged extending through a seating surface (5c) and which is capable of vertical movement relative to the base (2) so that contact tips (4a) of contact pins (4) can move in respective contact holes (5d). Latches (21) are arranged to be able to press the IC package on the seating surface (5c) of the adaptor (5) and a vertically movable regulator (7) is arranged at a selected position relative to adaptor (5) when stop surfaces (7e) of the regulator are engaged with a part (4e) of the contact pins (4) so as to regulate the position of the contact tips (4a) in the contact holes (5d).

Abstract: A semiconductor device is designed with a common supply voltage terminal (330). A plurality of standard cells (360-364), each having a plurality of leads (308,326) is connected to the common supply terminal. A plurality of connecting leads (322-324) corresponding to respective standard cells is coupled between at least two leads of the plurality of leads.

Abstract: A digital system (100) has two or more nodes (120, 130) and a communication channel (110, 111) for transferring a single stream of ordered data from one node to another. The communication channel (110) has a number of data links (110a-110g) for transferring a plurality of sub-streams of data in a parallel fashion in order to transfer more data than a single data link is capable of transferring. Receivers (132a-132g) each have synchronizing circuitry (200, 202) for synchronizing a byte clock and a frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that inherent data skew is eliminated.

Abstract: A quadratic phase interpolation method for synthesis of musical tones incorporates both phase and frequency measurements at the boundaries of a data frame using a weighted least square algorithm approach. The approach assumes that the true frequency and phase at the two ends of a data frame conform to a quadratic phase model and that exact match between measured phase and frequency with the quadratic model is not necessary because of the noise in the measurements.

Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.

Abstract: A method of AC induction motor speed control employing a rotor flux based MRAS (Model Reference Adaptive System) speed observer. Rotor flux-based MRAS speed observers develop two independent rotor flux estimates. The reference rotor flux estimate is based on the currents and voltages in the stator windings, and the adaptive estimate is based on the stator currents and the measured or estimated rotor speed. These two estimates are compared by taking the cross product between them, and this error signal is passed into a proportional-integral (PI) controller, which adjusts the speed until the flux estimates agree with one another. While this method is well-established, the estimator poles become lightly damped at high speeds and prone to stability problems. In this invention, the upper speed range of the rotor flux-based MRAS speed observer is extended by discretely or continuously modifying the gain/bandwidth parameters of the low-pass filter in the adaptive flux estimator as a function of estimated speed.

Abstract: An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: A system and method for generating an ultra-wide band communication signal having data occurring a specific frequencies precisely excised at baseband. The data to be transmitted is transformed into a function of time where the data to be excised can be removed in the time domain. After the data has been successfully removed in the time domain, the data is then transmitted in the frequency domain in which no data is transmitted at the frequencies where the data was precisely excised.

Abstract: A package for an integrated circuit includes a circuit board 122 for mounting the integrated circuit 114 having a first surface and a second surface, a connection device positioned on the first surface of the circuit board 122 for electrically connecting the integrated circuit 114 and the integrated circuit 114 being positioned on the second surface of the integrated circuit 114.

Abstract: A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.

Abstract: The higher order bit of the output from an address latch circuit is applied to a predecoder that operates a predecode signal to select a column select line and to a redundancy decoder to select a redundant column. The lower order bit of the address signal is generated by a burst address counter and applied to the predecoder. A comparison result for the higher order bit is calculated in advance at the redundancy decoder. When the lower order bit is applied to the redundancy decoder and the calculation of the comparison result ends, the redundancy determination is output from a redundancy determination unit.

Abstract: A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface of a semiconductor substrate (106). A deep trench plug (122) layer is deposited within the deep trench isolation structure (108). A shallow trench isolation structure (130) is formed where the deep trench isolation structure (108) meets the surface of the semiconductor substrate (106). A shallow trench plug layer (133) is deposited within the shallow trench isolation structure (130).