Abstract: A position sensor includes a stationary platform and a moveable platform. The position sensor further includes at least one beam coupling the moveable platform to the stationary platform. The at least one beam includes piezoresistive material that is positioned tolprovide an indication of a movement of the moveable platform relative to the stationary platform.

Abstract: Systems and methods are provided for limiting voltage to low-voltage devices employing a high-voltage supply. The systems and methods employ voltage limiting devices to bias cascode devices. The cascode devices are serially connected from a high-voltage supply to a low-voltage node. The voltage limiters are serially connected from the high-voltage supply to ground to bias the cascode devices. Current sources are connected in parallel with the voltage limiters except the one connected to ground. If the current sources are set to deliver substantially equal currents, then the order in which the cascode transistors are biased becomes nondeterministic, but the circuit continues to finction and the overall supply current is thereby minimized.

Abstract: A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.

Abstract: A driver (40) for supplying drive signals to a piezo element (48) of a milli-actuator device (21) in a mass data storage device (10) in a charge mode of operation has a first circuit (96, 98) for providing a charging current to a sense capacitor (58) in response to head position control signals. The first circuit is powered by a voltage supply (VM) that is referenced to a substrate potential, or a ground potential (AGND). A second circuit (104, 106) for mirroring a current in the first circuit at a predetermined mirror ratio (1x:Nx) to provide drive currents to the piezo element (48). The substrate potential may be, for example, an analog ground potential. If desired, the integrated circuit may also include a first switch (60) connected to selectively disable the first circuit (96, 98) a second switch (62) connected to selectively provide a feedback path from the second circuit (104, 106) to an input of the second circuit (104, 106).

Abstract: A circuit (48) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter (20) using an accumulator (52) for accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit (52) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit (120, 102′, 122) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update.

Abstract: Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The first approach uses a separate reset switch supply voltage, VRES, set to at least one threshold voltage below the sensing switch supply voltage, Vdd. The second approach uses a charge pump and level shifter to push the reset gate voltage at least one threshold voltage higher than a supply voltage common to both the reset and sense transistors.

Abstract: Echo cancellation in data communication between modems utilizes analog echo cancellation to lessen reduction of usable dynamic range of the received signal at the input to the analog-to-digital converter (DAC) in the receiver. Two digital-to analog (D/A) conversions are provided in the modem's analog front end (AFE). One generates the analog signal for transmission. The other generates an analog representation of a cancellation signal that is used to electronically cancel the echo before analog-to-digital (A/D) conversion of the received signal. A preferred embodiment utilizes multiplexed DAC architecture to emulate two DACs by sharing DAC circuitry between data paths of the two D/A conversions.

Abstract: An optical switch using an array of mirrors (608) to selectively reflect light from an input fiber (610) to either of a first output fiber (612) or a second output fiber (614). Each fiber is held in a ferrule (616) that aligns the fiber with a focusing device (618). The focusing device associated with the input fiber causes the beam of light to either collimate, diverge, or converge. The focusing device associated with each output fiber collects the beam of light for input into the output fibers. Light from the input fiber (610) strikes a first mirror, or group of mirrors, in the array (608) and is selectively deflected to a second mirror, or group of mirrors, associated with an output fiber (612, 614), by reflecting the beam of light from a retro-reflector (602) between the fibers. The second mirror receives the beam from the retro-reflector (602) and reflects it to the output fiber associated with the second mirror.

Abstract: A circuit for boosting an input voltage (VIN) to provide a low ripple output voltage (VOUT) regulates flow of current between a source of the input voltage (VIN) and a circuit node (17) in response to a feedback signal (16) representative of the output voltage (VOUT). A charge pump circuit operates to repetitively charge a pump capacitor (CPMP) to a voltage equal to the input voltage (VIN) and redistribute charge between the pump capacitor (CPMP) and a level-shifting capacitor (CLS) coupled between the circuit node (17) and an output conductor (15) conducting the output voltage (VOUT) so as to maintain the boosted output voltage (VOUT).

Abstract: A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a comparator (66) that compares a signal (104) indicating a value of the power supply to a ramp wave (69). An output of the comparator (66) is a signal containing a time width proportional to the output of the power supply. Additionally, a first comparator (90) compares the output voltage (42) to a first reference voltage (94). When the output voltage (42) exceeds the first reference voltage (94), the first comparator (90) changes state. A second comparator (88) compares the output voltage (42) to a second reference voltage (92). When the second reference voltage (92) exceeds the output voltage (42), the second comparator (88) changes state. The pulses are width modulated to first or second width limits in response to changes of output states of the first and second comparators.

Abstract: A method is provided for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a first material. A lower electrode is deposited over the adhesion layer and a ferroelectric layer is deposited over the lower electrode. The ferroelectic layer contains the first material. The ferroelectric layer is x-rayed and the x-ray fluorescence from the ferroelectric layer is detected for characterizing the ferroelectric layer.

Abstract: An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.

Abstract: A charge pump circuit is configured for suitably controlling the charging current in the charge pump capacitors. The charge pump circuit comprises an input current controlling circuit comprising a current limiting device for controlling the inrush current, and thus the charging current in the charge pump capacitors. The input current controlling circuit is configured to regulate the average voltage at the output of the current limiting device to correspond to the average voltage at the output of a pass device configured for regulating the output current. Accordingly, the total input current, and thus the charging current in the charge pump capacitors, can be suitably controlled at all times to significantly reduce the impact of any instantaneous charging currents.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer 60.

Abstract: A reference voltage generator having high-speed starting at a low power source voltage and with high stability and high precision, without substantially increasing the circuit area. NMOS transistors 10 and 12 form a current mirror circuit, with the same drain current I. PMOS transistors 14 and 16 form a current mirror circuit, and drain current I is fed to the current mirror circuit. Resistor 18 provides an offset between the source voltages of PMOS transistors 14 and 16. Start-up capacitor 22 is connected between gate/drain of NMOS transistor 10, which is connected as a diode, and the terminal of power source voltage VDD on the positive electrode side. And/or a start-up capacitor 24 is connected between gate/drain of diode-connected PMOS transistor 16 and the terminal of power source voltage VSS on the negative electrode side. In another embodiment PMOS transistors 25, 26 form a current mirror with the same drain current I.

Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.

Abstract: A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage of the buffer during a switching event, such that the voltage movement at the common emitter node of the differential pair output switch for the buffer circuit is decreased to substantially reduce distortion of an output signal associated with a DAC that employs the buffer circuit.

Abstract: To suppress undesired scattered light and leaking light so as to improve the optical function and reliability. In this DMD, as the address circuit of one cell, SRAM 12 is formed monolithically on the principal surface of silicon substrate 10, and, on said SRAM 12, reflective digital optical switch or optical modulating element 16 is formed monolithically as one cell made of three layers of a metal, such as aluminum, via oxide film 14. Each reflective optical modulating element 16 has bias bus 18 and yoke address electrodes 20, 22 as the first metal layer, torsional hinge 24, hinge supporting portions 26, 28, yoke 30, and mirror address electrodes 32, 34 as the second metal layer, and mirror 36 as the third metal layer. Optical absorptive and nonconductive film 40 is formed to cover a portion or all of the first metal layer and to cover underlying film (insulating film) 14. In addition, said film 40 is formed to bury hole formed on the surface of the third metal layer.

Abstract: A Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port. The voltage regulation circuit includes a first amplifier adapted to receive a reference voltage at a first input, having a second input, and having an output, and also a second amplifier having a first input coupled to an internal node, the internal node being coupled to the output of the first amplifier, the second amplifier having a second input adapted to receive a bias voltage and having an output. A pass transistor is provided having a source coupled to the voltage supply, having a drain coupled to the output port, and having a gate coupled to the output of the second amplifier, and a Miller compensation capacitor is provided coupled between the output port and the internal node.