Abstract: The present invention pertains to a type of frequency synthesizer which can correctly compensate for the ripple current. Frequency synthesizer 1 has PLL loop containing oscillator 31 and charge pump circuit 35. Also, the frequency synthesizer has compensating circuit 41 and correcting circuit 43. Said correcting circuit 43 has sense amplifier 44, up/down counter 45, and DA converter 40. The compensating circuit superimposes a compensating current onto the output current of charge pump circuit 35 which generates the control signal of oscillator 31, and it compensates for the ripple current contained in the output current. After the PLL loop is locked, sense amplifier 44 detects the ripple current with the superimposed compensating current, and based on the detection result, up/down counter 45 and DA converter 40 control compensating circuit 43, and the difference between the ripple current and the compensating current is reduced.

Abstract: A testing system for testing an integrated circuit device includes a test definition generator program which generates an initial test definition from information that includes test data. A checker program checks the initial test definition for compatibility with each of at least two different testers. Each of the testers includes a hardware interface, native software having driver routines for the associated hardware interface, and a compiler compatible with the driver routines. Each tester includes a converter program which has been compiled by a compiler other than the native compiler, and which converts the initial test definition into a modified test definition. The modified test definition is interpreted by an interpreter program, which has been compiled by the native compiler, and which controls the hardware interface through the native driver routines so as to carry out the test definition.

Abstract: An optical engine (15) for an SLM-type display system, which may be either a front or rear projection system (10, 20). The optical engine (15) provides for a high contrast, telecentric illumination angle to the SLM (33) without compromising brightness by vignetting due to offset in the pupil. The resulting offset pupil is converted to a telecentric, on-axis image by a relay path (34) between the SLM (33) and the projection lens (37). The relay path (34) places the image at an intermediate image plane accessible by a the projection lens (37), which permits the projection lens (37) to be telecentric without an offset pupil.

Abstract: A transport packet parser (42) includes a transport packet header decoder (50)for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packets satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.

Abstract: A capacitor (110) having a bottom plate (104) that includes undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).

Abstract: A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

Abstract: A low power Read Only Memory (ROM) bank accessing system with efficient bust muxing is provided. The memory access system includes separate pre-charge and pre-discharge circuits for each bit lines in the ROM bank. In a ROM bank read operation, the pre-discharge circuits and pre-charge circuits are activated and deactivated in accordance with the address of the targeted ROM bank. In an exemplary embodiment, only the pre-charge lines corresponding to the bit-line of the targeted ROM bank are pre-charged prior to the ROM read operation. Similarly, only the pre-discharge circuit corresponding to the bit lines of the targeted ROM bank is deactivated during the ROM read operation, permitting the remaining bit lines from storing residual charge.

Abstract: The present invention relates to a preamplifier circuit comprising a plurality of amplifier stages coupled together and operable to consecutively amplify a signal associated with a head of a hard disk drive. The preamplifier circuit further comprises a power delivery circuit operably coupled to the amplifier stages and operable to provide power to the amplifier stages in a substantially concurrent manner when the hard disk drive is transitioning from a write state to a read state. In addition, the circuit comprises a control circuit operably coupled to the amplifier stages, and operable to activate at least two of the plurality of amplifier stages in a generally consecutive manner after the providing of power to the amplifier stages. In the above manner a saturation of an output of the preamplifier circuit is avoided by preventing substantially a propagation of glitches through the preamplifier circuit and providing for a substantially fast write-to-read transition time.

Abstract: A flexible plating method by continuously controlling the hydrogen concentration of the plating bath by adding controlled amounts of hydrogen gas. The control of the hydrogen concentration is provided by selected distribution and number of nozzles and size of orifices; and predetermined pressure and duration of hydrogen gas flowing through the nozzles, wherein pressure and duration may be variable with time. The control of the hydrogen concentration is selected to provide a ramp-up phase, needed for a rapid plating start, followed by a saturation phase, for consistent plating stability. With metal layer plating under control, a robust, reliable and low-cost metal structure enabling electrical wire connections to the interconnecting copper metallization of ICs is formed. The structure comprises a layer of barrier metal, preferably nickel, that resists copper diffusion, deposited on the non-oxidized copper surface.

Abstract: A printer controller which renders the bands in a plane of a page to measure the resources required to render each band of the plane. The measured parameters are used to estimate the resources required to render bands in the other planes. As a strong correlation may exist in the complexity of the same relative band in different planes, the estimation may also be accurate. As a result, complex bands may be accurately pre-scheduled for rendering, and a printer may thus ensure that bits maps of even complex bands are timely available for printing.

Abstract: A display system 100 in which light from source (102) is focused onto a spinning color wheel (104). The spinning color wheel (104) creates of beam of light that changes from one primary color to the next in rapid sequence. The primary colored beam of light impinges a spatial light modulator (106), in this case a DMD. A controller (108) receives an input video signal and sends image data to the spatial light modulator (106) in synchronization with the color wheel (104)—image data representing the red portions of the image is sent during the period in which the red color filter is passing through the beam of light. The modulated red beam of light is focused onto an image plane (110) by projection lens (112) to form a red image. The process repeats as the green and blue filters pass through the path of the light beam. The eye of the viewer integrates the three primary color images giving the perception of a single full-color image.

Abstract: A four channel wireless network channelization scheme is described that is particularly usable in the ISM frequency band between 2400 MHz and 2483.5 MHz. The preferred channelization scheme permits access points to be set at one of four frequencies in the ISM band, not three as taught by the IEEE 802.11b standard. This channelization scheme takes advantage of the fact that only 20 MHz is typically needed between adjacent access point channels, not 25 MHz as is taught by the 802.11b standard. With four channels to choose from, a higher density of access points can be located thereby accommodating a higher density of users. The four channels preferably are 2407, 2427, 2447 and 2467 MHz. With this selection of channel frequencies and given the current FCC regulations, all four channels can be used to transmit an equal amount of power.

Abstract: Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively.

Abstract: An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node. An inverter coupled to the analog signal node drives common mode capacitors coupled between the output of the inverter and the respective negative and positive input nodes.

Abstract: A circuit assembly for doubling the voltage of a battery includes a charge pump (12) fed by the battery voltage and controlled by a clock generator (10). The supply voltage of the clock generator is the voltage output by the charge pump (12). The source/drain circuit of a field-effect transistor (P4) is inserted in the connection between the output of the charge pump (12) and the battery (26), the field-effect transistor (P4) being ON when its gate voltage is smaller than its source voltage. Connected to the gate of the field-effect transistor (P4) is the output circuit branch (N2) of a current mirror circuit (32) through which a limited small current is derivable from the gate to ground. An auxiliary charge pump (22) is provided which receives its supply voltage from the output of the charge pump (12) and which is likewise controlled by the clock generator (10). The voltage generated by the auxiliary charge pump (22) is placed on the gate of the field-effect transistor (P4) to switch it OFF.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: A method for isolatively coupling an input signal to an output signal, where the input signal is a first voltage differential, comprises three steps. Step one calls for generating a magnetic field that is indicative of the input signal in at least one magnetic sensor in an integrated circuit by generating a current through a conductor in the integrated circuit. The current is generated by applying the first voltage differential across the conductor, which is proximate the magnetic sensor. Step two requires generating a second voltage differential between two points of the magnetic sensor by providing a current through the magnetic sensor in a direction having a component transverse to the magnetic field. Step three calls for providing a signal indicative of the second voltage differential as the output signal, thereby isolatively coupling the input signal to the output signal.

Abstract: A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.

Abstract: A digital signal processing architecture is disclosed which is operable to receive a spread-spectrum/CDMA signal and perform the despreading operation thereon. The quadrature and in-band components of the signal (rI, rQ) are received and stored in a memory. The digital signal processor is operable to execute a plurality of single instructions in a sequential manner, one for each instruction cycle. Each of these single instructions cause data to be extracted from the memory, processed and an output provided in the form of a despread signal (RI, RQ). The process is performed in response to the generation of the single instruction by placing in the data path a DSP process that will perform the despreading operation by performing various multiplications, summations, and accumulations, all in a single instruction cycle.

Abstract: A method and apparatus is provided for performing an intelligent power-on-reset, and enabling the verification of a current voltage level with a reconfigurable brown out reset voltage level. In addition, the verification process may be selectively bypassed. Furthermore, the flash memory provides storage for the reconfigurable brown out reset voltage level and selected verification process enable/disable signal. In addition, the verification process occurs in a second phase during which some devices are released from reset mode and then those devices control the verification process.