Abstract: An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

Abstract: A differential driver includes two feedback loops 20 and 22, and two inverter pairs 24 and 26. The two feedback loops 20 and 22 regulate the source voltages for the two inverter pairs 24 and 26 to the reference voltages VREFHI and VREFLO. The two inverter pairs 24 and 26 switch the output load RL and CL between the two regulated voltages in response to the input voltages IN+ and IN−. The reference voltages VREFHI and VREFLO are created by a reference cell and set the output high and low voltages.

Abstract: A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.

Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A protective cover (10) for an optical device, such as a spatial light modulator or an infrared detector or receiver. The cover (10) has an optically transmissive window (11), which has a coating (12) on one or both of its surfaces. The coating (12) is made from a halogenated material, which is deposited to form a chemical bond with the surface of the window (11).

Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.

Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: Inventive methods and apparatus for use in simultaneously generating two or more pseudorandom noise (PN) sequences for spread spectrum communications are described. A data sequence generator includes a data access module and a multiplexing device. The multiplexing device has inputs to receive first counter values associated with a first demodulator and second counter values associated with a second demodulator. The multiplexing device has an output to provide, in an interleaved fashion, the first counter values and the second counter values to an input to the data access module. An output from the data access module provides, in an interleaved fashion, PN sequence data responsive to the first counter values and PN sequence data responsive to the second counter values for the first and the second demodulators, respectively. Preferably the data access module is a read-only memory (ROM) having the PN sequence stored therein.

Abstract: A low voltage, broadband differential operational amplifier which eliminates the long tail current source from the amplifier, thereby relieving the headroom requirements by a few tenths of a volt. An input common mode feedback circuit is used to overcome the problems arising from the removal of the long tail current source of prior art circuits. This circuit monitors the common mode feedback current and when the value of the current exceeds a specified range around the nominal amplifier bias current, an appropriate correction in the common mode input voltage is made. This novel amplifier will be valuable for use in pipelined analog-to-digital converter applications, as well as many other low voltage and/or portable applications.

Abstract: Two barrier layers are used for a via or contact. A thin CVD barrier (124) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole (106). A sputter etch is then performed to remove the CVD barrier (124) at the bottom of the via/contact. A second barrier (126) is deposited after the sputter etch. The second barrier (126) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: A current sense amplifier (10) for measuring current flowing through a sense resistor (12) coupled between first (11) and second (13) terminals, respectively, of the current sense amplifier, the current sense amplifier includes a first amplifier (18) having a first input (17) coupled by a first resistor (16) to the first terminal (11) and a second input (20) coupled by a second resistor (19) to the second terminal (13) and a bias circuit (30,24) coupled to the first input (17) of the first amplifier for causing the bias current to flow through the first resistor (16. A feedback transistor (26) is coupled to the output (22) of the first amplifier and the second input (20) of the first amplifier to cause a feedback current to equalize the voltages on the first (17) and second (20) inputs of the first amplifier and supply the feedback current to an output terminal (36) of the current sense amplifier (10).

Abstract: A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage Vcc rises, the predrive output voltage is lowered in response.

Abstract: A direct memory access function for servicing real-time events, ensures that any parameter reloads occur during times when the direct memory access channel is idle and guarantees completion before the channel begins active operation again. The direct memory access channel whose parameters are to be updated is disabled during the update cycle. This ensures that no requests are processed until the new parameters have been written to the direct memory access channel parameters. A second direct memory access channel may be used to reload the data transfer parameters permitting a self-modifying direct memory access function.

Abstract: Video compression coding with partitioning of data into motion vector data and texture data with reversible Golomb-Rice type codes for the data. Resynchronization markers separate the data types, and the reversible coding permits decoding in both forward and backward directions to minimize data discarded due to errors.

Abstract: An analog signal (VIN) is converted into a digital signal (24) by sampling the analog signal at a plurality of points in time to produce a sampled signal (32) which represents the analog signal. A filtering operation is advantageously incorporated into the sampling operation (102). The filtering operation filters the analog signal such that the sampled signal represents a filtered version of the analog signal. The digital signal is produced from the sampled signal.

Abstract: Digital subscriber modems (8, 15) for use in Asynchronous Digital Subscriber Line (ADSL) communications are disclosed. The central office modem (8) includes a digital transceiver function (10) and an analog front end function (12), where the analog front end function (12) is integrated into a single integrated circuit. According to the disclosed embodiments, the analog front end function (12) includes a transmit and a receive side. On the receive side, an impedance matching circuit (56) is coupled to the input of a programmable gain amplifier (54C). The impedance matching circuit (56) is controlled by the same control signals (C1, C2, C3) as used to select the gain of the programmable gain amplifier (54C), so that a constant input impedance is presented to the signal input (RXP), independent of the selected gain.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (782) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (781) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (71a) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.

Abstract: An aluminum hardmask (106, 214) is used for etching a dielectric layer (102, 210). A fluorine-based etch is used that does not etch the aluminum hardmask (106, 210). The aluminum hardmask (106, 214) is then removed by CMP.