Abstract: A circuit and method for providing drive currents to a polyphase dc motor are presented. The circuit (40) includes a circuit for generating a user-defined waveform first. signal in synchronism with a reference frequency signal. A reference frequency signal generator (62) generates pulses of a second signal at a reference frequency. A commutation circuit (56) combines segments of the first and second signals, and a circuit (64) is provided for applying the combined sinusoidal/trapezoidal waveforms to coils of the polyphase dc motor in a commutative sequence. Preferably, the user-defined waveform, when combined with the second signal, has approximately a sinusoidal/trapezoidal waveform.
Abstract: The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.
Abstract: An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper (28) incorporating self-timing logic (36) and a mux (32) is used to couple a single access memory core (30) to a memory interface unit (10). The memory interface unit (10) couples a central processing unit (12) to the memory wrapper (28). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle.
Abstract: A semiconductor processing apparatus (10) is disclosed which includes a process chamber (12) and at least one substrate support (18) disposed within the process chamber (12) operable to support a substrate wafer (20). The semiconductor processing apparatus includes at least one showerhead assembly (14) disposed within the process chamber (12) facing the substrate support (18) and has a showerhead plate (16). The showerhead plate (16) has a plurality of passageways (17) extending therethrough for directing process fluid toward a substrate wafer (20) disposed on the substrate support (18). A blocking assembly (21) is disposed within the process chamber (12), the blocking assembly has an active position (32) between the showerhead assembly (14) and the substrate support (18) to restrict the flow of process fluid between the showerhead assembly (14) and the substrate support (18).
Abstract: Transitions (e.g. high to low and/or low to high) associated with operation of the driver are employed to implement control, which can be applied as a pulse in response to an occurrence of the transition. The control operates to speed up the transition at the output of the driver, such as can reduce driver switching times and enable a corresponding increase in data transmission rates.
Type:
Grant
Filed:
April 2, 2002
Date of Patent:
September 30, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Fernando D. Carvajal, Mark W. Morgan, Srikanth Gondi
Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.
Type:
Grant
Filed:
January 14, 2002
Date of Patent:
September 30, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Craig T. Salling, Zhiqiang Wu, Che-Jen Hu
Abstract: A computerized system and method for reducing bond program errors in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave integrated circuit, by first collecting, on a master bonder, input data concerning bond x-y locations, alignment reference x-y locations, and alignment reference images from a master integrated circuit, then analyzing these data to construct a network of relationships between reference images and bond locations, and store data and relationships in a master file. Secondly, on a slave bonder, all this information is automatically retrieved and compared by a computer with input data concerning alignment reference images from a slave circuit. Thirdly, any discrepancy found is corrected by a computer to identify the new bond locations on the slave circuit. Finally, the slave bonder attaches the connecting bonds based on the computed correct bond locations.
Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.
Type:
Grant
Filed:
April 16, 2002
Date of Patent:
September 30, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
M. C. Ramesh, Feng Ying, Haydar Bilhan, Gary Lee, Yong Han, Ching-Yuh Tsay
Abstract: Given a system which detects simple events, one can define a complex event by constructing a list of sub-events. In order to recognize a complex event, the system keeps a record of the sub-events that have occurred thus far and the objects involved in these sub-events. Whenever the first sub-event in a complex event's sequence is recognized, an activation for that complex event is created. The activation contains an indication of the identity of the object involved in the event. The activation also includes an index initialized to one. If a newly detected event matches the next sub-event in any of the currently open complex events, the index for that complex event is incremented. If the index reaches the total number of sub-events in that complex event, the complete complex event is recognized. Thus any desired alarm is generated.
Abstract: An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by ‘swallowing’ or absorbing clock cycles of the available frequency source. Precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock.
Abstract: A method of constructing a semiconductor device 10 is disclosed which includes a reflow step. The device 10 comprises a conductive via 20 electrically connected to a conductive interconnect 28. The formation of interconnect 28 can result in damage to conductive via 20 including the removal of material within conductive via 20 to form a void 30. The metal reflow step involves heating the structure to a temperature short of the melting point of the conductive material forming the conductive via 20 and the conductive interconnect 28. The reflow step results in the migration of conductive material into the void 30 and a widening of the conductive interface between the conductive via 20 and the conductive interconnect 28.
Abstract: A method of testing the performance of real time DSP algorithms after customer code has been added and includes the steps of embedding a signature equation in the DSP code that calculates to a given signature value at the output of the DSP when running a test mode program through the DSP.
Abstract: An exemplary trimming circuit can be further simplified to include a single current source to provide for trimming of offset and temperature drift in a device, such as an op amp, voltage reference and the like. A single temperature-dependent current source is trimmed to a predetermined value, for example to zero, at a first temperature, and then the current from the temperature-dependent current source is used to trim output parameters, i.e., adjust the output variables, to a desired value at a second temperature. An exemplary trimming circuit comprises a temperature-dependent current source I(T), a current switch and a device to be, trimmed. The current switch is configured to suitably facilitate the trimming of the trimmed device through coupling of a fraction or multiple of the current signal from temperature-dependent current source I(T) to one or more offset-control terminals of the trimmed device.
Type:
Grant
Filed:
February 14, 2003
Date of Patent:
September 30, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Vadim V. Ivanov, Junlin Zhou, Wally Meinel
Abstract: Quiescent current drawn by an array of four-transistor loadless static random access memory (SRAM) cells is minimized by using a negative feedback loop to set a reference voltage, for the wordline driver, to a level which reduces the subthreshold current through the pass transistors to a level which is just barely sufficient to reliably retain data.
Type:
Grant
Filed:
December 31, 2001
Date of Patent:
September 30, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Andrew Marshall, Theodore W. Houston, Sreedhar Natarajan
Abstract: A reinforcing system for a bond which includes at least one dielectric layer or stack disposed under the bond pad. A reinforcing patterned structure is disposed in the dielectric layer or stack with the delectric filling the portion of the patterned structure from which the structure was removed after patterning.
Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit comprises a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.
Type:
Application
Filed:
September 3, 2002
Publication date:
September 25, 2003
Applicant:
Texas Instruments Incorporated
Inventors:
Rodney T. Burt, Haoran Zhang, Thomas L. Botker, Vadium V. Ivanov
Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
Type:
Grant
Filed:
June 14, 2002
Date of Patent:
September 23, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
Abstract: A switched capacitor integrator that shares a switched capacitor CAP1 at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor CAP1 with a first clock signal CK3; transferring an input voltage IN onto the capacitor CAP1 with a second clock signal CK1′; applying a reference voltage REF to a first end of the capacitor CAP1 with a third clock signal CK2; and coupling a second end of the capacitor CAP1 to the integrator with the third clock signal CK2 while the reference voltage REF is applied to the first end of the capacitor CAP1.
Abstract: An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).
Type:
Grant
Filed:
April 4, 2003
Date of Patent:
September 23, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Sameer P. Pendharkar, Philip L. Hower, Robert Steinhoff
Abstract: A method is provided for controlling a wafer polishing process. The method includes determining a polishing characteristic for a particular type of device from a set of measurements obtained from a wafer having a device of the particular type, and updating the polishing characteristic in response to polishing and measuring a wafer having a device of the particular type. The method further includes determining the polish rate of a polisher using a set of measurements obtained from a wafer polished on the polisher; and updating the polish rate of the polisher in response to polishing a wafer on the polisher and measuring the wafer. The method also includes determining a desired polishing time on the polisher for a wafer having a device of the particular type using the updated polishing characteristic of the device and the updated polish rate of the polisher.
Type:
Grant
Filed:
November 9, 2000
Date of Patent:
September 23, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Nital S. Patel, Gregory A. Miller, Christopher D. Guinn, Adriana Sanchez