Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.

Abstract: Given an incoming stream of interlaced video, data for each field is analyzed to detect a progressive frame cadence. If a progressive frame cadence is detected, a set of instructions is generated to instruct a de-interlacing unit which fields were mastered from the same progressive frame. The similarity in motion between two consecutive fields and the correlation between two consecutive fields is used to detect the presence of cadences and breaks in cadences. Breaks in cadences are continuously detected in order to characterize the source as video and prevent false detection of cadences.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: For combining light from different light sources in a light source, dichroic filters are displaced individually according to the physical arrangement of the light sources such that the reflected light from the dichroic filters is coincident in angle and space.

Abstract: A low drop out (LDO) voltage regulator (10) includes a pass transistor (MPpass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MPpa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (Rf) is coupled between the feedback conductor and the output conductor.

Abstract: The layered coding technique is employed to achieve the image quality scalability for video coding standards. The desired image quality scalability can be achieved by refining the image coefficients in subsequent enhancement layers. In most cases, the refinement coefficient consists of some binary information such as whether this coefficient is refined in this coding pass, whether this coefficient is positively or negatively refined, etc. Because it is generally difficult to code binary information efficiently with VLC (Variable Length Coding) technology, this disclosure introduces a method to code refinement symbol more efficiently with VLC by grouping the symbols of distinct binary elements.

Abstract: Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Abstract: According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.

Abstract: A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller being associated with one of the plurality of energy storage units, a balancing circuit between two of the energy storage units, the balancing circuit being controlled by at least one of the energy storage unit controllers, a serial electrical interface between the energy storage unit controllers for providing voltage isolated bi-directional communication, and a central controller in electrical communication with the energy storage unit controllers.

Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.

Abstract: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits corresponding to the pages in this row are masked so that they appear as non-prefetchable pages to the prefetch access generation engine preventing an access to any page in this memory bank. A powered down status bit corresponding to the memory bank is used for masking the output of the prefetch enable register. The prefetch enable register is unmodified. This also seamlessly restores the prefetch property of the memory banks when the corresponding memory row is powered up.

Abstract: An apparatus is provided. The apparatus comprises an input circuit, a startup circuit, and a current limiter. The input circuit is coupled to a first source and is adapted to provide a first voltage and a first current to a load having a capacitance. The startup circuit is coupled to the input circuit and to the first source, and the startup circuit includes a current source and a startup capacitor coupled in series with one another. The current limiter has a cascode circuit and a discharge circuit. The cascode circuit has a bias transistor and a power transistor coupled in series with one another to provide a second voltage and a second current to the load, where the bias transistor is coupled to a second source and where the bias transistor generally operates as source follower during startup. The discharge circuit is coupled to a node between the bias transistor and the power transistor of the cascode circuit and coupled to a node between the startup current source.

Abstract: In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes receiving a laser through a rotary diffuser. The rotational speed of the rotary diffuser may be continuously varied to reduce the effect of an image artifact in a light pattern. The image artifact may be caused by an imperfection in the rotary diffuser. The light pattern is projected on a display device.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

Abstract: A power supply circuit with low noise and low power consumption and a battery device using the power supply circuit. If a voltage VDD is higher than a prescribed voltage, a charge pump circuit 140A is operated in “½ mode” (a step-down ratio of “2”), steps down the voltage VDD, and outputs an intermediate voltage VCPO. Since the voltage VDD is stepped down, the intermediate voltage VCPO being input into a first LDO 135 is about half the case where no step-down is carried out, and the power being consumed in a MOS transistor Q11 (FIG. 3) of the first LDO 135 is greatly reduced. Therefore, the increase in power consumption of the first LDO 135 due to a voltage increase in the voltage VDD can be suppressed. Also, since the heat sink of the first LDO 135 can be reduced in size or omitted by the suppression of power consumption, the size and weight of the device can be reduced.

Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: The objective of this invention is to provide a boost circuit that reduces power consumption and prevents malfunctioning when the input voltage becomes greater than a target voltage for the output voltage. Control circuit module 5 sets both control signals HCNT2 and LCNT2 to low level “L” when the conditions “output voltage VBoost is higher than voltage OVREF” and “voltage (VIN+VOFFSET) is higher than output voltage VBoost” are satisfied. With this, in boost circuit module 7, switch SWH will be off and switch SWL will be on to forcibly switch to mode B. In mode B, because switch SWH is on, output voltage VBoost will be near input voltage VIN, and the power consumption can be reduced.

Abstract: An acoustic noise suppression filter including attenuation filtering with a noise-free estimate based on a codebook of line spectral frequencies.