Abstract: An apparatus is provided. The apparatus comprises a first current source and a second current source that charge and discharge a capacitor. Coupled between the capacitor and the second current source is a switch that can be actuated and deactuated by a controller. Preferably, the controller is coupled to the capacitor and receives a first threshold voltage and a second threshold voltage so that it can actuate the switch if the voltage across the capacitor is greater than the first threshold voltage and deactuate the switch if the voltage across the capacitor is less than the second threshold voltage. Additionally, there is a comparator that is coupled to the capacitor that compares the voltage across the capacitor to a reference voltage, and there is a a multiplexer that is coupled to the capacitor and that is coupled to the comparator.

Abstract: Embodiments of the invention provide time-domain link adaptation in power line communications. In one embodiment, the cyclic prefix length and position is adjusted with an OFDM symbol to overlap a periodic impulse noise pulse, thereby allowing the data carried in the symbol to be detected at a receiver. The cyclic prefix may be adjusted to provide a pattern that yields an integer number of OFDM symbols in one zero crossing period. The data rate used for the symbols overlapping the zero-crossing period may be zero or very low. A high data rate may be used for symbols outside the zero-crossing period because those symbols will not be affected by the periodic impulse noise.

Abstract: A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values.

Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.

Abstract: An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

Abstract: A method and a system are disclosed for maintaining a simultaneous communication between a first wireless station and both an access point and a second wireless station. The first and second wireless stations are associated with the access point, or only one of the wireless stations, but not both, is associated with the access point. The first wireless station gains an instance of medium access by using applicable medium access protocols. Once the first wireless station gains an instance of medium access, it transmits frames to the access point on an infrastructure network and to the second wireless station on the same infrastructure network or an ad hoc network. The overall air time must not exceed the maximum air time allowed for the instance of medium access. All transmitted frames must have a user priority mapped to the access category for which the instance of medium access was obtained.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ? the N concentration in a bulk of the annealed N-enhanced SiON gate layer ?2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.

Abstract: Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.

Abstract: In one embodiment, a gateway includes an interface, and a processor cooperatively operable with the interface to transmit and receive packet communications. The processor receives, over the interface, a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The processor transmits, over the interface, a notify of an observed event, the observed event indicating the backup battery status which is formatted according to the MGCP package protocol. In another embodiment, a call agent includes an interface and a processor. The call agent processor transmits a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The call agent processor also receives a notify of an observed event over the interface, the observed event indicating the backup battery status, which is formatted according to the MGCP package protocol.

Abstract: A LED drive circuit equipped with oscillator 18, up/down counter 20, and DAC 22 in order to drive multiple LEDs 10(1)-10(m) in a block. Up/down counter 20 carries out count-up/down operations in sync with clock CLK sent from oscillator 18 during the ramping up/down of pulse-lighting of the LEDs. DAC 22 converts counter count value DN into analog voltage signal VDAC and supplies it to the gate terminal of NMOS transistor 14 via low-pass filter 28 and buffer amplifier 24.

Abstract: A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

Abstract: A method for collecting data from semiconductor equipment includes selecting a plurality of data values to request from semiconductor equipment and assigning each of the data values to a chamber. Each chamber is associated with an engine that processes the data values in the associated chamber to detect a fault in the semiconductor equipment. The method also includes determining an order to receive the data values from the semiconductor equipment, and, after the order for the data values is determined, communicating a setup message requesting the semiconductor equipment to communicate the data values in the predetermined order. The method further includes receiving the data values from the semiconductor equipment and providing each of the received data values to the particular engine associated with the chamber of the data value.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Abstract: A method for film reconstruction includes identifying motion tear artifacts within a plurality of video fields of a stream of video fields. The motion tear artifacts identified by analyzing the video fields using fuzzy logic. The method also includes comparing the analysis of one video field to the analysis of an immediately preceding video field to determine whether there is a relatively high level of motion tear artifacts within the video field or a relatively low level of motion tear artifacts within the video field. The method further includes identifying a pattern of temporal periodicity for the comparisons. The method also includes determining the cadence of the stream of video fields based on the pattern of temporal periodicity.