Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.
Abstract: Asynchronous position pulses drive an interrupt to store pulse times via direct memory access; then synchronous sampling and analysis of the stored position pulse timings provides rate detection useful for feedback as useful in motor control.
Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.
Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.
Abstract: A decimated and interleaved multiplication table for finite fields as is useful in Reed-Solomon encoding computations. The generator polynomial coefficients determine the multiplication table content and ordering.
Abstract: A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask.
Abstract: A system is provided for precisely measuring a resistive load embedded in a potentially non-linear and capacitive Powered Device network which eliminates variable voltage from the measurement, decreases the capacitive settling times, and averages out system noise. A current and voltage (I-V) controller receives control voltages, applies constant load voltages to the resistive load in response to receiving the control voltages, and generates current flow voltages corresponding to current flowing through the resistive load. An integrating analog to digital converter (ADC) circuit receives the generated current flow voltages from the I-V controller and performs measurement cycles thereon. A control processor is operatively communicative with both the integrating ADC circuit and the I-V controller for controlling the measurements and calculations on the resistive load during first and second measurement cycles.
Abstract: An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to output a held signal, a buffer circuit to buffer the held signal to output a buffered signal, and a comparator circuit to compare the buffered signal with a reference voltage.
Abstract: Modem selection of Reed-Solomon codeword configuration to maximize error-corrected data rate given channel analysis. A lookup table of maximal codeword size given parity bytes and channel MSE allows precomputation.
Abstract: A method (40) of designing a circuit comprising a plurality of transistors (10, 46T, 60T). Each transistor of the plurality of transistors comprises an active region, a gate (G1, G2), a first source/drain (S/D1, S/D3) in the active region, a second source/drain in the active region, and at least one contact in each of the first source/drain and the second source/drain. The method comprises various steps. The method specifies a first set of distances for each transistor in a first set (10) of transistors in the plurality of transistors, wherein the first set of distances comprises a gate length (Lg), a gate width (Wg), and a distance representative of one or both of a first contact-to-edge distance (CTE1) and a first contact-to-gate distance (CTG1).
Abstract: The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a portable computer in a telecommunications environment. The invention comprises a coupled portable telephone(16)/interface module (40) that may be directly coupled to a portable computer (62). The interface module (40) portion of the invention includes a first interface (44) for coupling to an interface (34) on a portable telephone (16) and a second interface (58) for coupling to an interface (68) on a portable computer (62). The interface module (40) facilitates a direct connection between a coupled portable telephone (16)/interface module (40) and a portable computer (62).
Abstract: A WCDMA system and method of data communication allows a receiver to reliably achieve carrier frequency acquisition following turn-on without use of temperature compensation. Initial frequency acquisition is achieved by estimating the signal path position having the largest magnitude and then by estimating the phase difference associated with primary synchronization channels at a predetermined position within a single frame. The estimated phase difference is used to estimate a carrier frequency offset that can be used to adjust the local voltage controlled oscillator frequency, thereby acquiring the WCDMA communication signal carrier frequency.
Type:
Grant
Filed:
March 29, 2000
Date of Patent:
July 22, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Timothy M. Schmidl, Sundararajan Sriram
Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region (910) is used to pass variables to a subroutine and to hold values representative of a first portion of a program counter (1000). A system stack region (911) is used to hold values representative of a remaining portion of the program counter (1001) and to hold additional context information. The user stack region and the system stack region are managed independently so that software from a prior generation processor can be translated to run on processor (100).
Type:
Grant
Filed:
October 1, 1999
Date of Patent:
July 22, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Gilbert Laurenti, Walter A. Jackson, Jack Rosenzweig
Abstract: A computerized system and method for recreating illumination conditions in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave integrated circuit. First, images of illuminated alignment references of a master circuit on a master bonder are defined; these data are analyzed to construct relationships between reference images and bond locations; data and relationships are stored in a master file. Secondly, on a slave bonder, the master reference image data are regenerated so that the illumination conditions of the slave bonder, as based on images, are recreated. Thirdly, images of the slave circuit references are produced under the newly created illumination conditions, and the alignment references are compensated. Finally, the bonding locations of the slave circuit and the bonding program of the slave bonder are corrected so that connecting bonds can be attached onto the recomputed correct bond locations.
Abstract: A system for providing stability for a low power static random access memory (SRAM) cell (10) is provided that includes a wordline (14), a driver (34) and a mode selector (36). The wordline (14) is coupled to the SRAM cell (10). The wordline (14) is operable to select the SRAM cell (10) for read and write operations when activated and to de-select the SRAM cell (10) when de-activated. The driver (34) is coupled to the wordline. The driver (34) is operable to activate and de-activate the wordline (14). The mode selector (36) is coupled to the driver (34). The mode selector (36) is operable to provide a mode signal (44) to the driver (34) to place the wordline (14) into one of a plurality of modes.
Abstract: A system includes a serial bus 330, at least a first portion of which is formed on a circuit board. A first physical layer controller 322 is coupled to the first portion of serial bus 330. This physical layer controller 322 includes a register set with a plurality of eight-bit registers addressable by four-bit addresses. In this device, at least one of the seventh or eighth bits of the 0010 register is permanently programmed with a logical “1”. This physical layer controller is also backward compatible with a physical layer controller that conforms with IEEE-Std-1394-1995. The system also includes another physical layer controller 324, which may or may not be the same as physical layer controller 322, link layer controllers 314 and 316 and at least one processor (or controller) 310.
Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.
Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises decreasing a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. The method comprises forming an oxygen doped iridium layer and forming a ferroelectric dielectric layer thereover. During the formation of the ferroelectric, the oxygen doped iridium layer converts to an iridium oxide layer.
Type:
Grant
Filed:
December 21, 2001
Date of Patent:
July 22, 2003
Assignees:
Texas Instruments Incorporated, Agilent Technologies, Inc.
Inventors:
Sanjeev Aggarwal, Stephen R. Gilbert, Scott R. Summerfelt
Abstract: A group acknowledgment scheme permits a specified subset of a previously transmitted group of data frames to be acknowledged. In accordance with the preferred embodiment of the invention, a transmitting station sends a plurality of data frames to a receiving station and requests a single group acknowledgment frame from the receiving station, rather than an individual acknowledgment after each data frame. Also, the transmitting station's group acknowledgment request frame specifies or otherwise indicates which of the previously transmitted group of frames should be acknowledged and awaited by the receiving station. The group acknowledgment may apply to the entire group of frames, some but not all of the frames or just a single frame. Further, the receiving station's group acknowledgment frame defines the size of a buffer allocated to receive the next group of frame transmissions that are linked to the same group acknowledgment scheme.
Abstract: An access point in a wireless network transmits polling frames to node wherein the polling frame includes a traffic identifier (TID) value that corresponds to a particular stream or category of traffic. The polling frame prompts the receiving node to respond with its own data frames that correspond to the TID value. The node receiving the polling frame then responds to the polling frame with its own data frames that correspond to the TID value from the polling frame, if the node has any such frames with which to respond. Other features include the implementation priority levels that dictate which frames a node will transmit in response to the polling frame and a request traffic identifier (RTID) value that specifies whether or not the receiving node is to respond with frames that only correspond to the TID value in the polling frame.