Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

Abstract: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.

Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

Abstract: In a method and an amplifier for the compensation of unlinearities e.g. of the class D type, wherein an audio signal is pulse-width modulated, e.g. with a carrier wave signal in the form of a triangular signal to provide a pulse-width modulated small-signal, the so-called multiplicative error signals, which occur prior to the provision of a pulse-width modulated great-signal (7), are detected in a detector (10)). It is noted that the carrier wave signal could be analog as well as digital. The signal from the detector, which is derived on the basis of differences between the pulse widths of the small-signals and the pulse widths of the great-signals, is used for changing the carrier wave signal so that the amplifier gets a constant gain in the entire audio range and is thereby linearized.

Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

Abstract: Apparatus and methods for accessing a wireless telecommunications network by transmitting a random access signal. The random access signal includes a random access preamble signal selected from a set of random access preamble signals constructed by cyclically shift selected root CAZAC sequences. The random access signal may be one or more transmission sub-frames in duration, the included random access preamble sequence's length being extended with the signal to provide improved signal detection performance in larger cells and in higher interference environments. The random access signal may include a wide-band pilot signal facilitating base station estimation of up-link frequency response in some situations. Each of the plurality of available random access preamble sequences may be assigned a unique information value. The base station may use the information encoded in the random access preamble to prioritize responses and resource allocations.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light modulator (SLM) and a light incident on the SLM, shifting light modulator states of a first portion of light modulators to a second portion of light modulators, and placing a third portion of light modulators in the SLM into a performance degradation-reducing mode. The amount of shifting performed is proportional to the amount of change in the spatial relationship. The method allows for a change in light modulators used to modulate the light, thereby preventing the overuse of some of the light modulators, which may help to prevent degradation of the light modulators. The performance degradation reducing mode may help to further reduce or even reverse the performance degradation of the light modulators.

Abstract: Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery module with secure identity information includes: (1) a tamper resistant processing environment 200 located within the battery module 110 and (2) a key generator configured to generate a key based on an identity of the battery module 110 and cause the key to be stored within the tamper resistant processing environment 200.

Abstract: Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform block, and multiple transmit antennas. The antenna precoding block receives frequency coefficients from multiple data streams and distributes the frequency coefficients across multiple transmit signals in accordance with frequency-dependent matrices. The transform block transforms the precoded frequency coefficients into multiple time domain transmit signals to be transmitted by the multiple antennas. The frequency coefficients from multiple data streams may be partitioned into tone groups, and all the frequency coefficients from a given tone group may be redistributed in accordance with a single matrix for that tone group. In some implementations, the frequency coefficients within a tone group for a given data stream may also be precoded. In some alternative embodiments, tone group precoding may be employed in a single channel system.

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.

Abstract: An electronic data processing module (600) includes a context storage (640), cryptographic cores (615.i) adapted for acceleration of respective different types of encryption and decryption, and a mode control engine (610) responsive to a security context in said context storage (640) to operate one more selected said cryptographic cores according to a cryptographic mode at least partially specified by the security context. Other circuits and processes are also disclosed.

Abstract: A method and system of projecting images with high degrees of image offset while limiting the physical offset of the projection lens elements. The methods and systems provided limit the displacement of the optical elements relative to the optical axis of the display panel and enable a very thin, efficient projector.

Abstract: A method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes applying a global brightness change detection methods by computing the weighted prediction parameters, determining if the brightness change is different amount of change for the different regions, if the change is not different, calculate motion estimation and setting Refidx to 1 and setting Refidx is set to 0 when there is change, determining the best motion vector, motion vector cost and the best reference input, and determining a region-based weighted prediction with improved global brightness detection based on the motion vector data.

Abstract: A method and apparatus for camera calibration. The method is for disparity estimation of the camera calibration and includes collecting statistical information from at least one disparity image, inferring sub-pixel misalignment between a left view and a right view of the camera, and utilizing the collected statistical information and the inferred sub-pixel misalignment for calibration refinement.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.