Patents Assigned to Texas Instruments
  • Publication number: 20110316089
    Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
    Type: Application
    Filed: September 9, 2011
    Publication date: December 29, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Luis PACHECO ROTONDARO, Trace Q. HURD, Elisabeth Marley KOONTZ
  • Publication number: 20110316738
    Abstract: Embodiments of the invention provide a method of adjusting a bandwidth of receivers. A plurality of outputs from a correlator engine are combined. User dynamics are sensed. Bandwidth of one or more receivers are adjusted. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deric W. Waters, June Chul Roh, Sandeep Rao
  • Publication number: 20110317786
    Abstract: Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are created by shifting a feedback signal frequency by a plurality of first offset values and/or by shifting a transmission signal frequency by a plurality of second offset values. The feedback signals are compared to an input signal to identify the transmission channel response and/or a feedback channel response. A control signal is generated for a pre-distortion circuit to modify the input signal by an inverse of the transmission channel response. The composite system response is measured at a plurality of operating frequencies and at the plurality of offset values. The measurements are stored in a matrix and singular value decomposition is applied to the matrix of measurements to calculate the transmission channel response and feedback channel response.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Applicant: TEXAS INSTRUMENTS INC.
    Inventors: Fernando A. Mujica, Carson A. Wick, Lei Ding, Milind Borkar, Roland Sperlich
  • Patent number: 8084787
    Abstract: Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Rajesh Khamankar, Douglas T. Grider
  • Patent number: 8085940
    Abstract: Rebalancing of an audio signal refers to achieving a balance of perceived loudness, typically of right and left channels, given an unbalanced input. A flexible method to automatically rebalance an audio input signal is robust against noise in extreme cases through the individual channels combined in various ways as a function of the loudness ratio between input channels.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Steven David Trautmann, Atsuhiro Sakurai, Ryo Tsutsui
  • Patent number: 8085008
    Abstract: A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and variable resistors. The switch network is able to output a differential output signal and a common mode signal. The amplifier compares the common mode signal to a reference voltage, and the amplifier adjusts the magnitude of the current from the adjustable current source and the resistances of the variable resistors based at least in part on the comparison to adjust the peak-to-peak voltage swing of the output signal.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Kannan Krishna
  • Patent number: 8084312
    Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, P R Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider
  • Patent number: 8085958
    Abstract: Audio loudspeaker virtualizers and cross-talk cancellers and methods use a combination of interaural intensity difference and interaural time difference to define virtualizing filters. This allows enlargement of a listener's sweet spot based on psychoacoustic effects.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Trautmann, Atsuhiro Sakurai, Akihiro Yonemoto
  • Patent number: 8083961
    Abstract: A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 27, 2011
    Assignees: Tokyo Electron Limited, Texas Instruments Incorporated
    Inventors: Lee Chen, Ping Jiang
  • Patent number: 8085951
    Abstract: Methods, digital systems, and computer readable media are provided for determining a gain reduction parameter level for loudspeaker equalization by determining a noise score, an equalization effectiveness score, and an equalization non-effectiveness score for a candidate gain reduction parameter level, determining a composite quality score using the three scores, and designing a compensating filter for the loudspeaker using the candidate gain reduction parameter level if the composite quality score is better than composite quality scores of all other candidate gain reduction parameter levels.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Steven David Trautmann, Akihiro Yonemoto, Atsuhiro Sakurai
  • Patent number: 8085074
    Abstract: A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jayawardan Janardhanan, Samala Sreekiran, Sujoy Chakravarty
  • Patent number: 8085580
    Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Aswin N. Mehta
  • Publication number: 20110312144
    Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhiqiang WU, Xin WANG
  • Publication number: 20110311153
    Abstract: The method, system, and apparatus of source statistics based intra prediction type is disclosed. In one embodiment, a method includes classifying a four-pixel square block in an edge class (e.g., may include a DC edge class, a vertical edge class, a horizontal edge class, a diagonal edge class, and/or a planar edge class) based on an edge classifier, classifying an eight-pixel square block having the four-pixel square block and other four-pixel square blocks as a homogenous class if the four-pixel square block and the other four-pixel square blocks of the eight-pixel square block belong to the edge class, assigning a direction to the edge class of the eight-pixel square block, and determining an optimal intra-prediction type through the classification such that empirical testing of all possible ones of the edge class and the direction is avoided when the homogenous class is identified.
    Type: Application
    Filed: August 31, 2011
    Publication date: December 22, 2011
    Applicant: Texas Instruments Incorporated
    Inventor: Soyeb NAGORI
  • Publication number: 20110309440
    Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
  • Publication number: 20110309807
    Abstract: An electronic device for switched DC-DC conversion of an input voltage level into an output voltage level, comprising a first power switch and a second power switch, being connected in parallel and having a different gate width, and a driving stage that is configured to selectively drive the first power switch and/or second power switch depending on a load current output.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Applicant: Texas Instruments Deutschland GmbH
    Inventors: Michael Couleur, Neil Gibson, Christophe Vaucourt
  • Publication number: 20110310999
    Abstract: A method of performing overlap-and-add length for zero-padded suffixes. The method includes derotating received information symbol samples. The derotated received information symbol samples include a first set of derotated received information symbol samples and a second set of derotated received information symbol samples. The first set of derotated received information symbol samples are stored in a buffer. The second set of derotated received information symbol samples are provided to a received sample processing unit. The received zero-padded suffix samples are deroted. Based upon an overlap-and-add length, at least a fraction of the derotated received zero-padded suffix samples is added with at least a fraction of the first set of derotated received information symbol samples to produce multiple summed samples. The multiple summed samples is provided to the received sample processing unit.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William L. Abbott, Yehuda Azenkot
  • Publication number: 20110314301
    Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide systems for encrypting/decrypting data. Such systems include a hardware key, a memory, a hardware decoder and a message encoder. The memory includes an encoded encoding key that represents an original encoding key. The hardware decoder receives a portion of the encoded encoding key and decodes the portion of the encoded encoding key using the hardware key to recover a portion of the original encoding key. The message encoder receives a data set and the portion of the original encoding key and encodes the data set using the portion of the original encoding key to create an encoded data set.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 22, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Garry R. Elder, Ramanujam Thodur
  • Publication number: 20110309523
    Abstract: An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Yoshimi TAKAHASHI
  • Publication number: 20110310869
    Abstract: A method of communications for a coexisting wireless network including a wireless combination (combo) device communicating via a first wireless network and second wireless network, and a first wireless device on the first network. During an activity interval for the second network (i) a transmit (Tx) time interval is longer in duration than a Tx packet duration and/or (ii) a receive (Rx) time interval is longer in duration than a Rx packet duration to provide remaining time. A frame aggregated packet is used on the first network that includes a plurality of data packets and a dummy packet or spoofing so that the frame aggregated packet is extended in time or indicates an extension sufficient to overlap the Tx time interval or Rx time interval. The combo device transmits or receives an acknowledgement (ACK) on the first network during the activity interval for the second wireless network.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ARITON E. XHAFA, YANJUN SUN, RAMANUJA VEDANTHAM