Abstract: A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a hinge/support structure formed from a second substrate. The hinge/support structure includes a recessed region and a torsional hinge region. The mirror is coupled to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region.

Abstract: A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock signal from a source coupled to the sample-and-hold circuit. The frequency of the jittered clock signal is less than frequency of the received RF signal. The random number appears at the output of the sample-and-hold circuit.

Abstract: Systems and devices for dynamically scaled charge pumping are presented. Example embodiments of the disclosed systems of dynamically scaled charge pumping enable regulation of the output voltage at a particular ratio and to dynamically control the ratio based on the input voltage. A charge pumping circuit is enabled by an oscillator. The charge pump oscillator is enabled by the output of a comparator. The comparator compares an input voltage to a comparator voltage, which is a divided version of the output voltage. The output voltage is referenced to a regulated voltage and the comparison voltage is divided between the two voltages by a resistor divider. The regulated voltage remains flat until the input voltage equals the reference voltage. At that point, the regulated voltage will begin to rise and follow the input voltage. Before the reference voltage is reached, the output voltage equals the input voltage multiplied by the resistor divider ratio.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.

Abstract: Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). The EVSE and EV exchange a Pulse Width Modulation (PWM) signal on the pilot wire to control charging operations of the EV. Data communications may also be transmitted on the pilot wire, such as between transmit and receive modems. The modems transmit communication signals either continuously, without regard to the state of the PWM signal, or only when the PWM is in an off-state. If transmitting while PWM is on, the modem needs a large coupling impedance and/or a large signal injection. To transmit only when the PWM is off, the modem may use a blocking diode in the coupling circuit or may synchronize to the pulses in the PWM signal.

Abstract: A connection formed by a copper wire (112) alloyed with a noble metal in a first concentration bonded to a terminal pad (101) of a semiconductor chip; the end of the wire being covered with a zone (302) including an alloy of copper and the noble metal in a second concentration higher than the first concentration. When the noble metal is gold, the first concentration may range from about 0.5 to 2.0 weight %, and the second concentration from about 1.0 to 5.0 weight %. The zone of the alloy of the second concentration may have a thickness from about 20 to 50 nm.

Abstract: A method for video compression and a video encoder. The method for video compression includes finding a coefficient relating to inter-coded block with a biggest absolute value, determining the number of non-zero coefficients when the absolute value is less that 2, determining the number of non-zero coefficients is less than a threshold, and setting the coefficients to zero when the non-zero coefficients is less than the threshold.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.

Abstract: Relayed nodes communicate with a target hub using a relaying node in a two-hop star network. The relayed nodes transmit a first encapsulating frame having a payload that comprises an encapsulated frame. The first encapsulating frame is formatted as a one-hop communication between the relayed node and the relaying node. The encapsulated frame is formatted as a one-hop communicate between the relayed node and the target hub. The relaying node generates a second encapsulating frame having a payload that comprises the encapsulated frame from the relayed node. The second encapsulating frame is formatted as a one-hop communication from between the relaying node and the target hub. The target hub sends frames to the relayed node in a similar manner through the relaying node. The target hub and relaying node communicate during scheduled uplink, downlink, or bilink allocations, and the relaying node and the relayed node communicate during scheduled bilink allocations.

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract: An integrated circuit includes logic configured to generate scrambling sequences, each based on a different scrambling seed, for a smart-utility-network data packet communication. A Hamming distance between any two scrambling sequences is half the length of a PSDU of the data packet or greater.

Abstract: Techniques for managing a video encoding pipeline are disclosed herein. In one embodiment, a video encoder includes a multi-stage encoding pipeline. The pipeline includes an entropy coding engine and a transform engine. The entropy encoding engine is configured to, in a first pipeline cycle, entropy encode a transformed first macroblock and determine that a predetermined slice size will be exceeded by adding the entropy encoded macroblock to a slice. The transform engine is configured to provide a transformed macroblock to the entropy coding engine. The transform engine is also configured to determine, in a third pipeline cycle, coding and prediction mode to apply to the first macroblock, based on the entropy coding engine determining, in the first pipeline cycle, that the predetermined slice size will be exceeded by adding the encoded macroblock to a slice.

Abstract: An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected at a junction node. Each of the cascoded pairs receives a corresponding level-shifted signal representing the input signal, and generates corresponding driver signals on driver nodes which are coupled to the output node. The driver circuit includes a capacitor connected between one of the driver nodes and the junction node. The capacitor enables the corresponding driver signal to be generated to reach a desired voltage quickly. The output impedance of the output buffer with which the output signal is launched is reduced and more closely matched the impedance of the path on which the output signal is provided. Signal quality of the output signal is thereby improved.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position is also estimated. Then a signal from at one or more satellites may be received. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a GNSS receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked.

Abstract: A system for communicating protocol layer processing information is disclosed herein. A transmitter includes a protocol layer header generator that generators a header for a first protocol data unit. The header generator provides a first header comprising a first sequence number field that determines the order in which a receiving entity present the first data unit to higher protocol layer. The sequence number field varies in length. A receiver includes a protocol layer header parser that parses a header of a first protocol data unit. The header parser parses a first header comprising a first sequence number field that determines the order in which the first data unit is presented to a higher protocol layer. The sequence number field varies in length.

Abstract: A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power supply node and ground. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter that assists its change of state in a write operation. In other embodiments, a single power switch transistor gated by either a word line or a column select signal may be used.