Abstract: A CRC-based adaptive halting turbo decoder applies a CRC code to identify internally generated information sequences. The information sequences are encoded with the CRC code and can be substantially identified by only the parity part. New information sequences are generated during each iteration and used to estimate the state of the convergence. The CRC-based adaptive halting turbo decoder is halted when the information sequences generated in two contiguous iterations produce identical parity bits. Memory storage requirements for the adaptive halting are reduced since only the parity bits are stored.

Abstract: The current passing in a main trans-conductor circuit is compared in analog domain with a reference current. If the passing current exceeds the reference current, another trans-conductor circuit may be switched on to cause the effective area of trans-conductor circuits to be increased. Using such a feature, the trans-conductance value may be maintained substantially constant without substantially increasing power.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory cell, a toggle bit is sensed from a toggle memory cell, and the sensed data bit is transferred to an IO line in either inverted form or non-inverted form according to the sensed toggle bit. The sensed data bit and the toggle bit are then inverted and restored to the data and toggle memory cells so as to mitigate or reduce cell imprint.

Abstract: A system and method is provided for translating a wide common mode voltage range into a narrow common mode voltage range. The system and method extend the common mode voltage range of functional devices beyond the supply rails of the functional device, while keeping the differential signal loss to a minimum. The system and method translate a common mode input signal from a wide common mode voltage range into a narrow common mode voltage range utilizing a feedback technique.

Abstract: Distortion optics are used to efficiently couple a spiral color wheel and an orthogonal modulator. Light 602 from a light source enters an aperture in a reflective end of a recycling integrator rod 604. The light travels through the rod and exits the end of the rod adjacent a sequential color filter 606, shown as a spiral color wheel. The shape of the light beam 608 exiting the integrator rod 604 is determined by the shape of the exit aperture of the integrating rod 606. The exit aperture of the integrating rod 606 typically is formed by a reflective exit aperture on the exit face. A cross section of the light beam 608 exiting the sequential color filter includes several bands of filtered light, one for each of the filter segments of the color wheel illuminated by the light beam. The curvature of the color bands makes it difficult for a row addressed spatial light modulator to efficiently use the light.

Abstract: A method of waveform generation using a VLSI digital tester unit without an arbitrary waveform generator. A software application produces a series of vectors to drive a digital tester unit from a set of datapoints which defines a waveform needed in the test program. The set of datapoints can be generated in a test simulator such as SPICE or can be generated by digitizing the arbitrary waveform needed in a test program. The vectors describe the number of resistors of a pseudo arbitrary waveform generator (PAWG) circuit to be driven high in order to reproduce the desired waveform for input into the device under test. The software also determines the resolution, e.g., 5 ns, of the waveform.

Abstract: A technique is disclosed which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger operational amplifiers. In accordance with one aspect, the op amp cells can be suitably coupled in parallel to provide a larger operational amplifier. This paralleling aspect can be facilitated by connecting the respective negative and positive inputs of a predetermined number of input gm stages together, connecting the outputs of a predetermined number of output gm stages together, and connecting a predetermined number of intermediate internal nodes between the input gm stages and the output gm stages together, without the occurrence of saturation of the internal nodes. In addition, the input and output characteristics of operational amplifier can be suitably improved.

Abstract: A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards frame boundary parameters to the coprocessor (15). Parameter registers (26) in coprocessor (15) store synthesis parameters for iteratively deriving amplitude and phase values for each sample point within a data frame. Adders (28, 30, 32) generate current amplitude from one addition, and current phase value from two additions, with the results stored back into parameter registers (26). A sine function calculator circuit (34), which may use a CORDIC technique, receives the current amplitude and phase values, and generates a digital component signal for the current sample point for one of the sinusoids. Digital component signals are accumulated at the sample point in a data sample buffer (40) and output at an output (44).

Abstract: A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).

Abstract: A method of determining a capacitance for use in a circuit simulation is provided. The method may include determining a test structure capacitance of a test structure, simulating a design structure, extracting a design structure capacitance of the simulated design structure, and calculating a parasitic capacitance of the design structure. Calculating the parasitic capacitance may comprise deducting the test structure capacitance from the design structure capacitance.

Abstract: Disclosed is an optical component, which comprises a prism element adjacent to a lens element, where the two elements are separated by a small air gap. In disclosed embodiments, the elements have adjacent and parallel surfaces which are substantially planar and which, with the small air gap, operate through Total Internal Reflection (“TIR”) to direct light beams that strike the planar surfaces. Light beams that strike at less than the critical angle are internally reflected, while light beams which strike at greater than the critical angle pass through. The TIR surfaces thereby separate the desired optical signals from the spurious ones. The combined TIR prism lens operates as a single and integrated component which directs desired light beams to a reflective optical processing element such as a Spatial Light Modulator and which focuses the processed light beams as they leave the combined TIR prism lens.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current path resistor (160,158), and a biasing circuit (162,164) in series. Each side of the MR head 42 is connected between a respective one of the current path resistors (158,160) and the biasing circuits (162,168). A shunt resistor (170) is connected between the control transistors (154,156) and the current path resistors (158,160) in each of the current paths. When the control transistors (154,156) are not conducting, the current path resistors (158,160) and the shunt resistor (170) shunt the MR head (42).

Abstract: A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may independently generate a sampling clock based on an analog signal, and sample the analog signal at time points specified by the sampling clock to generate multiple data bits. A multiplexor is used to provide a bit after the transition instead of a bit generated by the recovery circuit. As all bits after transition are recovered, data encoded in an analog signal may be recovered accurately.

Abstract: Disclosed is a mounting system and method in which symmetrical springs are used about a collar in a gimbal system to capture an assembly of a ball and an optical or other type of component. Once captured within the mounting system, the ball/component assembly can pivot until an optimal alignment is reached. Once the optimal alignment is reached, the ball/component assembly is fixed using laser welding.

Abstract: A method for removing sacrificial layers during the process of fabricating micro-mechanical devices with a solution of super-critical carbon dioxide. A mixture of super-critical carbon dioxide with other solvents, co-solvents and surfactants is used during the process to remove sacrificial layers. The disclosed method has many advantages over the prior art, including a reduction of capillary forces that can damage the free-standing micro-mechanical superstructures, an absence of plasma induced damage caused by ashing operations, and a reduction in the use of environmentally sensitive chemicals. Another advantage of the disclosed process is that the swelling of the photoresist layers is minimized. The disclosed method may be used to remove sacrificial layers that were deposited during the process of fabricating micro-mechanical devices. The method is also effective to remove a protective recoat layer that is deposited over a micro-mechanical device after it has been fabricated.

Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

Abstract: A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106). The thin liner (110, 210, 310) smoothes the sidewalls of the trench (108) and/or via (106) and reduces resistivity. The thin liner may comprise an organic or inorganic dielectric (110) or metal (210,310). A copper interconnect structure (116, 216, 316) is then formed over the thin liner (110, 210, 310).

Abstract: A conductive via pattern (110) between the uppermost metal interconnect layer (Mn) and next underlying metal interconnect layer (Mn−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).