Abstract: A rapid sensor calibration technique applied prior to each Sensor 9 measuring a beverage in which water (zero Brix), at same temperature as beverage, is drawn from a Water Supply 3 via Valve 6 and passed over the fixed optic Sensor 9 in order to reference out any sensor temperature changes or beverage temperature changes or sensor surface fouling by the dispensed beverage. This technique of continuous and multiple calibrations, provides an enhanced “beverage dispensing system” calibration beyond that achievable using known calibration methods associated with automatically sensing and controlling beverage quality for soft drinks from a fountain dispenser using, for example, water at a specific temperature to initially calibrate Sensor 9, or using a high quality beverage, from a bottle, for example, at a known Brix level to initially calibrate Sensor 9.

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of realtime information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.

Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal.

Abstract: A computer (10) uses a TTL-to-LVDS converter board (34) coupled to a graphics controller (32). The graphics controller (32) outputs video information using TTL logic levels. The TTL-to-LVDS converter board (34) is coupled to the graphics controller using a cable and is preferably located proximate the graphics controller (32) to minimize cable length. A display (20) is coupled to the TTL-to-LVDS converter board (34).

Abstract: A video surveillance system that implements object detection and event recognition employing smart monitoring algorithms to analyze a video stream and recognize the interaction of people with cars. The system forms a reference image consisting of the background of the scene viewed by the video camera. The system forms a foreground difference image between the current image and an updated reference image including any stationary cars. The system detects any objects other than any stationary car in the scene. The updated reference image is formed by forming a background difference image between the current image and the reference image. Any detected object is examined to determine if it is a car object. Upon initial detection of a stationary car object, the system forms a reference car image of a portion of the current image corresponding to the position of the stationary car.

Abstract: A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the elongated projection. A gate structure is operable to control the access channel to selectively couple the first terminal to the second terminal.

Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

Abstract: A semiconductor reliability test structure (10) is formed on a face of a semiconductor substrate. The test structure (10) includes a chain of a plurality of long test links (12) formed of a first semiconductor material, where the plurality of long test links (12) is alternately interconnected by a plurality of short connecting links (14) formed of a second semiconductor material. The test structure (10) further includes first and second bond pads (20, 22) coupled to the first and second ends of the chain, respectively.

Abstract: A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two passes through a block of instructions. A match of signatures generated from the two passes through the block of instructions indicates valid operations, a mismatch indicates an error. A software assisted solution compares a signature generated from one pass through a block of instructions with a signature pre-calculated by a compiler or with a one of a set of pre-calculated signature selected at run time. This is useful for digital signal processor design using deep-sub-micron devices and dynamic logic for superior system performance by enabling detection of errors that can result from the low noise-immunity in circuits using higher impedance smaller devices with low threshold voltage and dynamic logic.

Abstract: A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one embodiment the first thickness is about half the second thickness. The transistor also includes a collector region 342 over the buried region, a base region 396 within the collector region, and an emitter region 422 within the base region.

Abstract: A single-DAC, multiple sample/hold conversion circuit includes a digital-to-analog converter and a plurality of sample/hold circuits each including an output amplifier, first and second hold capacitors coupled to inputs of the output amplifier and to terminals of and first and second sampling switches. An operational transconductance amplifier (OTA) has a first input coupled to an output of the digital-to-analog converter. A feedback switch is coupled between a second input of the OTA and the output of the output amplifier. A control circuit closes the feedback switch, first switch, and second switch of a sample/hold circuit selected according to an address input supplied to the control circuit.

Abstract: A digital system is provided with an interface circuit for interconnecting two modules in different clock domains. The interface circuit can selectively respond to a request signal from a remote source and immediately de-assert a ready signal in response to either a rising edge or a falling edge of the request signal asynchronously to a local clock signal. When an internal circuit connected to the interface circuit has completed a requested operation, the interface circuit asserts the ready signal. The ready signal is de-asserted and asserted in a glitchless manner so that the remote module can respond to the ready signal asynchronously to a remote clock signal.

Abstract: A socket (10) has a cover (14) pivotably mounted to a base (12). The base is formed with a seat (12a) for mounting a semiconductor device on a contact mounting plate (18). A locking mechanism (20) for locking the cover in the closed position includes an over center linkage mechanism interacting with a locking pin (20a). In a modified embodiment, the locking mechanism is provided with a pivotable locking member (27) to provide either manual or automated operation. The cover (14) of socket (10) also comprises an integrally formed heat sink. In another embodiment (10′), a separate heat sink (30) is independently mounted on the cover (28) provided with an aperture through the cover in which the heat sink is slidably mounted.

Abstract: A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

Abstract: One aspect of the invention is an integrated circuit (613)comprising a current source (611) coupled to voltage source (610) and an output load (635). The integrated circuit (613) further comprises a charge pump (600) coupled to the current source (611) at a first node (612) and to the output load (635) at a second node (620) and a recirculation circuit (650) coupled to the first node (612) and the second node (620). The recirculation circuit (650) is operable to limit to a known value the current that flows between the second node (620) and the output load (635).

Abstract: An improved reticle (20) and method of using it to expose layers of wafers for large integrated circuits (10). The integrated circuit (10) is designed so that nonrepeating patterns are laid out in perimeter areas, distinct from the center area containing contiguous repeating patterns. The reticle (20) is patterned with multiple masks (21-23), with different masks representing the repeating and nonrepeating patterns. The mask (22) representing the repeating pattern may then be stepped and illuminated separately from any mask (21, 23) representing a nonrepeating pattern.