Abstract: The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: An embodiment of the invention is a doped region within the silicon substrate 20 of an integrated circuit where the silicon substrate 10 separates the doped region into at least two sub-regions 40, 50. Another embodiment of the invention is a method of manufacturing an integrated circuit where any logic element is formed in a doped region. The doped region containing the logic element is separated into at least two sub-regions 40, 50 by the silicon substrate 10 of the integrated circuit.

Abstract: An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond the gate section on opposite sides thereof. A dielectric layer has an upper surface spaced above the upper ends of the side walls. Contact openings are created through the dielectric layer, so as to expose surface portions on the source and drain regions. Conductive contacts are formed in the contact openings. The portions of the side walls which project above the gate section permit misalignment of the contact openings, without exposing any portion of the gate electrode during formation of either contact opening.

Abstract: A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104).

Abstract: The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: Apparatus for flexibly locating the data page on which the peripheral registers are located. External hardware contentions are eliminated because the peripheral registers can be relocated anywhere in the system address space. Hardware design is therefore much more flexible. Further, because the present invention allows peripheral registers to overlay internal data memory, data transfers can be carried out between data and peripherals using the same data page pointer. No intermediate pointer loading operations are required and memory operations to the peripheral registers can be carried out at maximum speed. The present invention allows peripheral registers to overlay data memory in a manner that permits the overlaid memory to be recovered and used for other purposes. Processor program code can be designed to overlay internal data memory with the peripheral registers while performing data transfers between the data memory and the peripheral registers.

Abstract: An embodiment of the instant invention is a method of forming a conductive barrier layer on a dielectric layer, the method comprising the steps of: providing the dielectric layer (112 of FIG. 7d) having a top surface, a bottom surface, and an opening extending from the top surface to the bottom surface, and including a conductive plug (704 of FIG.

Abstract: The objective of the invention is to provide an inductive load driving circuit that can prevent occurrence of surge voltage. Output transistor 5 and auxiliary transistor 6 are connected in parallel with each other. When output transistor 5 is turned off, auxiliary transistor 6 is kept on. The energy remaining in inductive load 26 is consumed with current flowing to auxiliary transistor 6. When the output transistor is turned off after the current flowing to output transistor 5 has attenuated, since the counterelectromotive force occurring in inductive load 26 is small, the counterelectromotive power can be clamped by the threshold voltage of auxiliary transistor 6.

Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device may have a significant relative gain and is constructed with no additional mask steps.

Abstract: An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than desired, implanting to form the source and drain of the PMOS transistor with dopant that moves faster during annealing such as Boron and then wet etching the polysilicon gates down to the shorter length such as the final length before implanting with the faster dopant such as arsenic.

Abstract: An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.

Abstract: An integrated circuit having an interconnect layer (104) that comprises a first barrier layer (106) and an aluminum-based layer (108) overlying the first barrier layer (106). An aluminum-nitride layer (112) is located on the surface of the aluminum-based layer (108). AlN layer (112) is formed by converting a native aluminum-oxide layer to AlN using a plasma with H2 and N2 supplied independently rather than supplied together in the form of ammonia.

Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.

Abstract: An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.

Abstract: A method for using pulse-width modulation in displays. A series of PWM sequences is established. Each subsequent sequence clears the previous sequence before it, eliminating the need for a separate clearing reset at the end of the previous sequence. This allows for use of spoke bits in color-sequential systems. In non-color sequential systems and rapid color-switching systems it allows the sequence for one frame to flow directly into the sequence for the next frame.

Abstract: A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials (110/112/114) with high selectivity to the carbon hardmask (122).

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized direct memory access unit. The external direct memory access controller may update source or destination address for a next occurrence of an event type by adding an offset or updating an address pointer to a linked list. The centralized direct memory access unit queues data transfer parameters on a priority channel basis and stalls the external direct memory access controller for a particular priority level it the corresponding queue is full.