Abstract: A modem with built-in transmission line diagnostic capability is presented. Said built-in line diagnostics are capable of determining said transmission line's length and detecting the presence of any bridge taps. Said built-in diagnostics have an advantage of not requiring any specialized or expensive hardware and can be added to an existing modem without significant redesign work.

Abstract: A system and method facilitate estimating noise in a received signal. The received signal includes a plurality of data tones. Noise is estimated for a selected subset of data tones for each data burst, such that noise estimates for all data tones can be computed over a plurality of data bursts. As a result of spreading the noise estimates over more than one burst, the overall computations associated with obtaining the noise estimates can be reduced based on the size of the respective subsets. The updated data tone noise estimates further can be employed in subsequent processing, such as in beamforming calculations.

Abstract: The present invention provides a multi-function buffer system for use in a peripheral storage device system, as well as a peripheral storage device system having a multi-function buffer system. The buffer system comprises a multi-purpose memory component which may be adapted for use as scratchpad and/or instruction storage accessible by a controller processor, as well as for buffering information being transferred between the peripheral storage device and a host computer system.

Abstract: Prior art attempts to reduce the power consumption demands of dual infrared transceiver laptop computer designs have.included enabling and disabling infrared ports at the user level. This solution requires the computer user to be involved in decision making with respect to infrared peripheral device discovery, and adds complexity to the overall infrared communications experience. Post connection dual IrDA port power management implements the infrared transceiver power down decision making in software, based upon activity inputs from the infrared link controller. Minor changes to the link controller at its device driver improve the user experience and the power consumption in dual IrDA port configurations.

Abstract: A computer system (10) includes a plurality of hot-plug sockets (30-33), each of which can be selectively uncoupled from a bus (59) during normal system operation, in order to facilitate insertion or removal of module (36). A clock signal (PCLK) is generated at one of two different frequencies, and at system power-up a clock arbitration circuit (47) is responsive to modules which are present for specifying a speed of the clock signal. A hot-plug controller circuit (18) can selectively uncouple one of the hot-plug sockets from the bus during normal operation to facilitate insertion or removal of a module, and also facilitates a determination of whether clock speed requirements of an inserted module are compatible with the current clock speed. The selected socket is recoupled to the bus only if the inserted module is compatible with the current clock speed.

Abstract: The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor speed. The fan controller circuit comprises a current detection circuit and a motor speed determination circuit. The system further comprises a fan driver circuit operable to drive a motor at a duty cycle based on the PWM control signal from the fan controller circuit. The fan driver circuit comprises a current sink circuit operable to draw current from the PWM control signal when the PWM control signal is high and when the motor reaches a predetermined position. In the addition, the current detection circuit is operable to detect the current draw on the PWM control signal and provide an indication signal to the fan speed determination circuit associated with such detection. Further, the motor speed determination circuit is operable to determine the speed of the motor based upon a timing associated with successive current draw detections.

Abstract: A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.

Abstract: A combined system and method for computer-controlled bonding and testing of wire connections between integrated circuit chips and substrates, and for automatically adjusting the bonding parameters in response to said testing, comprising the steps of forming a wire connection between said chip and said substrate under computer control to create wire attachments and a wire span; testing said wire connection automatically under computer control to generate test data; and automatically adjusting the bonding parameters of subsequent wire connections responsive to said test data, whereby the number of faulty bonds is reduced to near zero and bonding production downtime is substantially eliminated.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range of precompensation is extended beyond limits imposed by the duty cycle of the clock signal. Catastrophic failure of the write precompensation circuit is prevented by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The range of a write precompensation circuit is extended by ORing the clock and the clock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: A method and structure of recovering a network time-base for radio data demodulation after an IDLE period of data communication gauges a local low frequency oscillator versus the high frequency local oscillator to compute the IDLE time as an equivalent number of low frequency oscillator clock periods. Depending upon the high frequency oscillator value, the accuracy of the gauging will directly determine the IDLE period duration versus the gauging period duration in order to keep an acceptable gauging error related to the sampling errors.

Abstract: A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface for engaging a workpiece and establishing ultrasonic coupling thereto. At least one crystal oscillator is ultrasonically coupled to the carrier and operates at a resonant frequency in an ultrasonic band which is indicative of a desired polishing depth of the workpiece, such as the endpoint of polishing. A detector circuit provides an output signal which is representative of an output level of the crystal oscillator. A processor circuit receives the signal from the detector circuit and provides a signal to the polishing machine when the amplitude of the signal from the detector circuit indicates that the desired polishing endpoint has been reached. A number of crystal oscillators can be spatially arranged on the carrier to establish a local polishing depth detection array.

Abstract: A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog output signal (s(t)) based upon a digital baseband signal (S) from a digital signal processor (42). The digital-to-analog conversion function (50) includes first and second &Sgr;&Dgr; modulators (46, 48), each of which are controlled by a sampling clock generated by a dual frequency divider (47) controlled by the first &Sgr;&Dgr; modulator (46). A sampling latch (49) samples the digital baseband signal synchronously with the sampling clock. The second &Sgr;&Dgr; modulator (48) selects an oversampling multiple that is applied to a digit filter (52) along with the sampled signal from the sampling latch (49). The digital filter (52) reconstructs a digital signal from the sampled value and the oversampling multiple that is the equivalent of that reconstructed by the decimation of an over sampled signal.

Abstract: Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck at either high or low logical value. The PLL is initialized if the output is stuck. Once initialized, the PLL may resume generating a desired output clock signal.

Abstract: A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

Abstract: A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

Abstract: A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of a wire line pair (20) includes an interface (212, 292) to the wire line pair (20) and a signal converter (214, 290) with a terminal coupled to the interface. An on/off-hook detector(300) drives an impedance analyzer function (304) that is able to measure transmission line parameters based on the current line characteristics of the wire line pair (20). A control logic block (310) performs the actions required to adapt to a new line conditions of the wire line pair (20) and rapidly adapt to the new on/off hook condition.

Abstract: A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing.

Abstract: An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion includes a relatively small capacitance, coupled in series with a resistance which is sufficient to effect substantial limiting of the magnitude of any leakage current that may flow through the capacitor.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.