Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device may have a significant relative gain and is constructed with no additional mask steps.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.

Abstract: A method for using pulse-width modulation in displays. A series of PWM sequences is established. Each subsequent sequence clears the previous sequence before it, eliminating the need for a separate clearing reset at the end of the previous sequence. This allows for use of spoke bits in color-sequential systems. In non-color sequential systems and rapid color-switching systems it allows the sequence for one frame to flow directly into the sequence for the next frame.

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of realtime information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.

Abstract: A rapid sensor calibration technique applied prior to each Sensor 9 measuring a beverage in which water (zero Brix), at same temperature as beverage, is drawn from a Water Supply 3 via Valve 6 and passed over the fixed optic Sensor 9 in order to reference out any sensor temperature changes or beverage temperature changes or sensor surface fouling by the dispensed beverage. This technique of continuous and multiple calibrations, provides an enhanced “beverage dispensing system” calibration beyond that achievable using known calibration methods associated with automatically sensing and controlling beverage quality for soft drinks from a fountain dispenser using, for example, water at a specific temperature to initially calibrate Sensor 9, or using a high quality beverage, from a bottle, for example, at a known Brix level to initially calibrate Sensor 9.

Abstract: A voltage regulator circuit that provides the current necessary to drive an output driver during transients and maintain low output impedance, while having a much better dropout voltage than a single source follower gain stage includes: an output driver 22; a source follower 34 for controlling the output driver; a localized feedback gain loop coupled to the source follower 34; and an amplifier 24 for controlling the source follower 34.

Abstract: An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than desired, implanting to form the source and drain of the PMOS transistor with dopant that moves faster during annealing such as Boron and then wet etching the polysilicon gates down to the shorter length such as the final length before implanting with the faster dopant such as arsenic.

Abstract: An integrated circuit having an interconnect layer (104) that comprises a first barrier layer (106) and an aluminum-based layer (108) overlying the first barrier layer (106). An aluminum-nitride layer (112) is located on the surface of the aluminum-based layer (108). AlN layer (112) is formed by converting a native aluminum-oxide layer to AlN using a plasma with H2 and N2 supplied independently rather than supplied together in the form of ammonia.

Abstract: An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.

Abstract: A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials (110/112/114) with high selectivity to the carbon hardmask (122).

Abstract: An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized direct memory access unit. The external direct memory access controller may update source or destination address for a next occurrence of an event type by adding an offset or updating an address pointer to a linked list. The centralized direct memory access unit queues data transfer parameters on a priority channel basis and stalls the external direct memory access controller for a particular priority level it the corresponding queue is full.

Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.

Abstract: A computer (10) uses a TTL-to-LVDS converter board (34) coupled to a graphics controller (32). The graphics controller (32) outputs video information using TTL logic levels. The TTL-to-LVDS converter board (34) is coupled to the graphics controller using a cable and is preferably located proximate the graphics controller (32) to minimize cable length. A display (20) is coupled to the TTL-to-LVDS converter board (34).

Abstract: A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

Abstract: A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the elongated projection. A gate structure is operable to control the access channel to selectively couple the first terminal to the second terminal.

Abstract: A semiconductor reliability test structure (10) is formed on a face of a semiconductor substrate. The test structure (10) includes a chain of a plurality of long test links (12) formed of a first semiconductor material, where the plurality of long test links (12) is alternately interconnected by a plurality of short connecting links (14) formed of a second semiconductor material. The test structure (10) further includes first and second bond pads (20, 22) coupled to the first and second ends of the chain, respectively.

Abstract: A video surveillance system that implements object detection and event recognition employing smart monitoring algorithms to analyze a video stream and recognize the interaction of people with cars. The system forms a reference image consisting of the background of the scene viewed by the video camera. The system forms a foreground difference image between the current image and an updated reference image including any stationary cars. The system detects any objects other than any stationary car in the scene. The updated reference image is formed by forming a background difference image between the current image and the reference image. Any detected object is examined to determine if it is a car object. Upon initial detection of a stationary car object, the system forms a reference car image of a portion of the current image corresponding to the position of the stationary car.