Abstract: A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated signals, including phase and amplitude modulated signals such as quadrature amplitude modulation (QAM) information. The carrier recovery circuit (35) includes a phase detection function (40), preferably realized by way of programs executed by a digital signal processor, that generates a derivative signal (g(x″)) based upon a summation of a complex function of a corrected input signal (x″) over some or all of the possible points in the modulation constellation. In one embodiment of the invention, the derivative signal is an exact evaluation, considered over the sum of all points in the constellation; in another embodiment of the invention, only four small magnitude points, at relative quadrature phases, are included in the summation.

Abstract: A method as well as a bias generator and associated output circuit architecture (300) that protects output skew voltage capabilities for the associated output circuit (304) to a greater extent than that achievable using presently known circuit architectures and techniques. A voltage level detector (306) comprising a differential-pair circuit detects bias voltage levels and provides a signal (308) to skew adjusting assist devices (310, 312) when the bias voltage levels get close to a “choking off” voltage level. The signal (308) turns on the skew adjusting assist devices (310, 312) to assist the skew adjusting devices (102, 104).

Abstract: To address the need for enhanced real-time analysis, Texas Instruments Inc. has developed a standard embedded infrastructure for its DSPs that provides unique visibility into real-time program execution. Integrated with TI's Code Composer Studio development environment, this infrastructure consists of two components: 1) DSP/BIOS, a tiny target-based run-time system that captures event and statistical information for the application and uploads it to the host (via a standard physical link such as JTAG) as the application executes in real-time; this DSP/BIOS system is integrated with the target application (C or DSP assembler); 2) Scope, a suite of host-based tools that allows designers to visually trace, monitor, and probe the DSP application as it executes in real time.

Abstract: An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connectes to the functional input and output signal leads, core circuitry (120, 122, 124), and interconnect wires and circuits (103) connecting the input and output circuits and the core circuitry. The integrated circuit further includes an addressable test port (105, 115, 135) for each core circuitry. Each test port is connected to its respective core circuitry and to the interconnect wires and circuits. External test signal leads (106) connectes to each test port.

Abstract: In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22, 24) arranged on a surface of the semiconductor chip (10) and contact areas (26, 28) on the chip carrier (12) by means of an anisotropically conducting film (16) or an anisotropically conducting paste (16), a pressure die (18) is used for the application of the pressure to the chip (10) with an adjustable pressing force against the chip carrier (12). A counter-pressure support (14) accepts the chip carrier (12) with the semiconductor chip (10) arranged on it with the interposition of the anisotropically conducting film (16) or the anisotropically conducting paste (16). An elastic body (20) is arranged either between the pressure die (14) and the semiconductor chip (10) or between the chip carrier (12) and the counter-pressure support (14).

Abstract: This is a system and method of processing multiple video streams for a computing device. The system may comprise: a central processing device; a communications bus connected to the central processing device; an input device connected to the central processing device by the communications bus; an output device connected to the central processing device by the communications bus; a multiple video stream processor connected to the output device by the communications bus; and at least two video streams connected to the multiple video stream processor. In addition, the video streams may include input from a CD-ROM, PCMCIA cards, storage devices, peripherals on docking stations and other communications devices. Moreover, multiple video processing device may include input from zoom video ports, buffers and digital-to-analog converters, and a reformatting device. Other devices and systems are also disclosed.

Abstract: Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length of a leading code in the compressed data stream is then determined based on the leading position of the specified value.

Abstract: A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via.

Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.

Abstract: A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C filter, adjustable resistance and reactance assemblies are coupled in series. The resistance assembly has multiple parallel signal paths sharing a common input and output. Each signal path includes a prescribed electrical resistance and a digital switch to selectively enable and disable the resistance. Between the common input and output, the signal paths provide a collective resistance which varies depending upon which switches have been activated. The reactance assembly is similar to the resistance assembly, with capacitors or inductors instead of resistors. A digital controller selectively activates the switches to adjust the assemblies' respective resistance and reactance.

Abstract: A highly efficient and simple power conversion circuit (300) having zero voltage switching (ZVS) includes a novel switch timing technique, such that the need for an leakage inductor connected in series with the primary circuit of the converter and rectifier diodes is eliminated. A switch timing circuit (351) located in an output side circuit (350) enables the use of the natural stored magnetic energy in the output side circuit (350) to drive the critical switching transitions to accomplish soft switching for all of the switches (314-317) in a full bridge forward converter (300) for all transitions. This power conversion circuit (300) includes a full bridge circuit (310) having plurality of switching devices (314-317) that intermittently couple the primary winding (327) to the input of the power converter (300). A transformer (326) couples to receive power from the full bridge circuit (310) into its primary winding (327).

Abstract: A print head motor control system uses a desired function of print head position versus time and a measured print head position to form an error signal. The print head controller forms a motor drive signal from the sum of a first term corresponding to the square root of the absolute value of the error signal and a second term corresponding to a dead band signal having a predetermined slope if said error signal exceeds a predetermined value. The desired function of print head position versus time may be formed by double integrating a desired function of print head acceleration versus time. The print head motor control preferably also includes a velocity loop subtracting a print head velocity estimated from the measured print head position from the sum. The print head motor control is preferably implemented using a microprocessor.

Abstract: Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.

Abstract: A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond onto a bond pad of an integrated circuit by first obtaining a first image of said bond pad before bond attachment, then determining the coordinates of the center of said pad. Second, the bonder is instructed to attach a ball-shaped wire bond to the center of said pad. Next, a second image of said bond pad is obtained after bond attachment; this second image comprises an image of the ball-shaped portion of the bond and an image of the wire portion of said bond. The coordinates of the center of the ball-shaped portion of the bond are obtained by computer processing of the first and second images. The coordinates of the bond center and the pad center are compared, creating information for quality control of the bonder instruction and the bonding process.

Abstract: A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank test membrane having a conductive coating or a matrix of conductive lines formed thereon. Once a die bond pad configuration is known, the test membrane can be configured for the die bond pads by using a laser under software control to define connection pads correlating to the die bond pads and also to define interconnecting conductive traces from the connecting pads to contact pads that can be connected to test equipment. In one embodiment, the laser operates to ablate a continuous conductive coating, so as to form conductive pads and traces. In another embodiment, the laser is used to cut various lines in a matrix of conductive lines, so as to define conductive paths from the bond pads to the contact pads for connection to the test equipment.

Abstract: A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second charge pump coupled to an output of the phase detector. A capacitor is coupled to an output of the first charge pump, a first bias circuit coupled to the capacitor, the first bias circuit having a differential output. A voltage controlled ring oscillator has a plurality of differential inventer stages, each having a first input coupled to a first output of the first bias circuit and a second input coupled to a second output of the first bias circuit. A second bias circuit is coupled between the capacitor and the first bias circuit, an output of the second bias circuit being coupled to an input of the first bias circuit and to an output of the second charge pump. The PLL circuit exhibits a stable damping factor with respect to frequency.

Abstract: A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control circuit (106) and a output stage bias reference circuit (108). The input gain stage (102) includes differential inputs (IN−, IN+) and differential outputs (A1, B1). The output stage (104), having control transistors, connects to each differential output (A1, B1) of the input stage (102). and a quiescent current control circuit (106) deriving common mode feedback control signal (VCS1) from the differential outputs (A1, B1) and voltage bias node (D1). A quiescent current control circuit (106) derives the common mode feedback control signal (VCS1) to maintain the voltage of the input gain stage transistors (M3, M4) at a desired level.

Abstract: A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti—Al—N including at least 1% of aluminum.

Abstract: A mixed-signal integrated circuit (12) having compensation for leakage through an ESD cell (16) at an external terminal of a reference voltage is disclosed. A reference voltage generator circuit (14) generates a reference voltage that is low-pass filtered by an on-chip resistor (Rf) and an off-chip capacitor (Coc). The ESD cell (16) is connected at the terminal node between the resistor (Rf) and the capacitor (Coc), as is an ESD compensation circuit (20, 20′, 20″). The ESD compensation circuit (20, 20′, 20″) includes a dummy ESD cell (29) that is physically matched to the ESD cell (16), and a current mirror biased in a direction corresponding to the direction of the expected leakage through ESD cell (16). The ESD compensation circuit (20, 20′, 20″) ensures that very little of the leakage current through ESD cell (16) is conducted by the filter resistor (Rf), so that changes in this leakage current over temperature or bias conditions does not modulate the reference voltage.

Abstract: A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation.