Abstract: A data storage cell that is stable on standby but upsets on read. Standby stability is achieved without read and restore. In one embodiment, the leakage current is balanced by manipulating the transistor widths and lengths, making the subthreshold current of the pass transistor greater than that of the drive transistor. A write-back during the read cycle compensates for the read upset.

Abstract: A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A windows-type display (160, 170, 180, 190) displays sections of computer code (160a, 170a), as well as numerical values representing power usage (160b, 170b). Next to each section of code, some sort of visual representation of power usage is displayed, such as a bar of a bar graph (160c, 170c). Alternatively, the code can be highlighted if power usage exceeds a given threshold, or comments can be provided next to the code for optimizing power usage.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: A micro-BGA style package for semiconductor device comprises a semiconductor chip and a package substrate. The semiconductor chip includes a plurality of conductive pads. A plurality of transistor circuits are formed upon the semiconductor chip. The package substrate has first and second sides. A plurality of conductive terminals are formed on the first side of the package substrate. At least one of the terminals is electrically coupled to at least one of the conductive pads. A plurality of contacts are formed on the second side of the package substrate. A plurality of traces are disposed on the first side of the package substrate. Each trace provides at least part of an electrical coupling between at least one of the terminals and at least one of the contacts. The traces are formed from a copper based metal having a tensile strength of more than about 60 kg per mm2.

Abstract: A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or IMD (110).

Abstract: A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28) in a baffle plate (27). After the chamber has been cleaned, several test wafers are etched under conditions which are equivalent, except that a different gas pressure is used for each wafer. The effective etch rates are measured from these wafers, and used to extrapolate a reference curve (141) representing effective etch rate relative to pressure. During subsequent production use of the chamber, a similar procedure is periodically used to generate a test curve (142). The peak values (143, 144) of the reference and test curves are compared (147) to monitor process drift within the chamber. The peak values of respective curves obtained from two or more similar chambers can be compared to evaluate performance differences between the chambers.

Abstract: An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide “pole-zero” compensation to the output stage amplifier circuit.

Abstract: A reduced-leakage current dynamic circuit (10) is disclosed that includes a logic circuit (30), a pre-charge transistor (32), and a standby transistor (40). The logic circuit (30) is coupled to an internal output node (50). The logic circuit (30) includes a plurality of logic transistors (60 and 62) having a low threshold voltage. The pre-charge transistor (32) is coupled to the internal output node (50). The pre-charge transistor (32) is operable to provide a pre-charge voltage at the internal output node (50) and has a standard threshold voltage. The standby transistor (40) is coupled to the internal output node (50). The standby transistor (40) is operable to provide a standby voltage at the internal output node (50).

Abstract: A method for generating charge sharing test vectors for a circuit generates a first test vector (120) and a second test vector (122). The method provides a test model (98) including a logic cell (10) and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method generates a first test vector (120) for the test model (98) having an input pattern to discharge nodes of the logic cell (10) and evaluate discharge AND gate (102) to a logic level 1. The method generates a second test vector (122) having an input pattern to evoke the worst charge sharing behavior for the logic cell (10) and evaluate charge sharing AND gate (104) to a logic level 1.

Abstract: For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG.

Abstract: An acoustic reflector (48) is applied over a thin-film piezoelectric resonator (41, 61) which is supported on a semiconductor or semiconductor-compatible substrate (42, 62) of a microelectronic device (40, 60), enabling an encapsulant (49) to be applied over the reflector-covered resonator without acoustically damping the resonator. In one embodiment, alternating high and low acoustic impedance layers (51, 53 . . . 55) of one-quarter wavelength thicknesses constructively reflect the resonating wavelength to make an encapsulant in the form of an inexpensive plastic molding compound appear as a “clamping” surface to a resonator (41) peripherally supported over an opening (43) on a silicon substrate (42). In another embodiment, an encapsulant- and reflector-covered resonator (61) is mechanically supported above a second reflector (68) which eliminates the need for peripheral support, making substrate (68) also appear as a clamping surface.

Abstract: A socket (10) has a cover (14) pivotably mounted to a base (12). The base is formed with a seat (12a) for mounting a semiconductor device on a contact mounting plate (18). A locking mechanism (20) for locking the cover in the closed position includes an over center linkage mechanism interacting with a locking pin (20a). In a modified embodiment, the locking mechanism is provided with a pivotable locking member (27) to provide either manual or automated operation. The cover (14) of socket (10) also comprises an integrally formed heat sink. In another embodiment (10′), a separate heat sink (30) is independently mounted on the cover (28) provided with an aperture through the cover in which the heat sink is slidably mounted.

Abstract: A color splitting prism assembly (100) comprised of three prisms. Each a dichroic filter at an interface (112) between a first and second of the three prisms reflects a first primary color component of a white light beam passing through the prism assembly. The first primary color component is directed to a first modulator (118). The remaining portions of the white light beam enter a second prism (108) and strike a second dichroic filter at the interface between (124) the second and third prisms. The second dichroic filter separates a second primary color component from the white light beam leaving a third primary color component to travel through the third prism (110) to a third modulator. The second primary color component of the white light beam is directed to a second modulator (128).

Abstract: An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and ringing while allowing for higher data rates. The discharge circuit is turned on after the head voltage or current reaches an overshoot condition. In preferred embodiments, the discharge circuit includes variable discharge capability by selecting one or more parallel drive transistors or varying a variable delay in the discharge circuit or any combination of both variables. Both can be controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: A Reed-Solomon encoding device is provided that can handle multiple RS (Reed-Solomon) codes using different field generation polynomials. The encoding device uses a first Galois field transformation that transforms source data into a specified Galois field on the basis of a first Galois field transformation parameter. The transformed source data is received by an encoder that performs encoding processing using a selected multiplication coefficient set. A second Galois field transformation is used for performing an inverse transform of the encoded data on the basis of a second Galois field transformation parameter. A parameter output is used for outputting the first Galois field transformation parameter, the second Galois field transformation parameter, and the selected multiplication coefficient set. The parameter output generator is operable to be loaded with transformation parameters and multiplication coefficients selected from a plurality of transformation parameters and multiplication coefficients.

Abstract: A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes.

Abstract: A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces.