Abstract: A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted. As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.

Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

Abstract: A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input signal and one for detecting its falling edge. The input signal is typically assumed to have some known nominal clock rate, but its exact frequency and phase (timing of transitions) are not known. Each of the two metastability resolvers comprises two branches of cascaded flip flops, each clocked off the rising edge and falling edge of a fast clock. Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.

Abstract: An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.

Abstract: A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting the digital signal from the time domain to the frequency domain and feeding the digital signal to a frequency domain equalizer having variable coefficients for flattening the converted digital signal. The frequency domain equalizer includes a gain corrector coupled to the FFT to compensate the channel frequency rolloff and make each tone approximately the same amplitude before phase rotation and a phase rotator portion responsive to the output of the gain corrector to track small channel variation. Also included is circuitry for updating the coefficients of the frequency domain equalizer, preferably in the form of a slicer for controlling the frequency domain equalizer by feeding back an error signal thereto. The error signal is preferably fed back to the phase rotator portion of the frequency domain equalizer.

Abstract: A device for phase alignment between a data signal and a main clock signal, characterized by the fact that, from a main clock signal, it has some means of generation of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal, some means 10 of dividing the input data signal by sampling of said signal by said clock signals in order to obtain data signals with a length equal to said fraction of a period of said main clock signal, observation window 14 of said sampled data bits, said window 14 having a length equal to a data bit of the entering signal, a set of pipelines 16 for parallel processing using an algorithm of the signals transmitted by the observation window in view of retrieving data signals, and device 18, 19 for drift compensation.

Abstract: Signal conversion apparatus and method with coarse and fine digital to analog converters. The output of the coarse DAC has a high gain to support wide voltage swings, while the fine DAC has a low gain to support accurate tracking control. The two outputs are combined in an analog summing junction. The apparatus and method may comprise a low pass filter connected to the coarse DAC output. The filter may be switched off during large changes to provide rapid system response, and switched on during position holding to attenuate noise from the coarse DAC. The apparatus and method may comprise a pre-charging capacitor in the filter, wherein the capacitor may be pre-charged when the filter is off, reducing the switch transient when the filter is switched on.

Abstract: A protective device (3) for a hermetic type electromotively driven compressor (1a) includes a protector assembly (30) having a housing (32) with an electric current fuse (34) which detects a predetermined over-current. The housing (32) comprises an electrically insulating skirt member (31) formed so as to block a conductive part on the side facing an external connection terminal. By forming the electrically insulating skirt member (31) of housing (32) for a hermetic type electromotively driven compressor, insulation distance between a conductive part such as the electric current fuse (34) and an external conductive part such as a metal wall part (21) is set to be 9.5 mm or more.

Abstract: A circuit (10) for braking a polyphase dc motor (12) includes a circuit (38) for producing an output signal indicating that the motor has slowed at least to an actual rotational speed and a braking circuit (42-44, 26-28) to brake the motor (12) when the output signal indicates that the motor has slowed at least to an actual rotational speed. The circuit (38) for producing an output signal indicating that the motor (12) has slowed at least to an actual rotational speed includes a first counter (70) for counting pulses of a speed signal, which may be a standard tach signal. The first counter (70) produces a first output when the first counter (70) reaches a first predetermined pulse count. A second counter (72) counts clock pulses from a clock generator (48) to produce a second output when the second counter (72) reaches a second predetermined pulse count.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: Detection of excessive negative offset of a condition responsive sensor such as a pressure responsive full Wheatstone bridge element (10) and circuitry associated therewith is obtained by taking the sensor's output signal, preferably after the signal has been compensated for both gain and offset and comparing (Q1) the signal (Vx) with a reference voltage (VREF1) selected to reflect an unobtainable stimulus input condition and driving the compensated signal to a fault level when the compensated signal exceeds the reference voltage.

Abstract: A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of the amplifier. This input receiver (30) includes a complementary self-biased differential amplifier (10) and a dynamic hysteresis voltage reference circuit (20), wherein the complementary self-biased differential amplifier (10) has an input node (Input2), a reference output node (S2), and a dynamic voltage reference node (VDYNREF). The dynamic hysteresis voltage reference circuit (20) connects between the reference output node (S2) and the dynamic voltage reference node (VDYNREF) to provide a reference voltage (Vref) at the dynamic voltage reference node(VDYNREF). The reference voltage (Vref) serves as a threshold for the complementary self-biased differential amplifier (10), such that the output transitions from high-to-low and low-to-high when the input is equal to the reference voltage (Vref).

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of lead-free solder on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: A motion artifact reduction system (10) includes a series of cinematic feature image frames (IFm, IFm+1)captured at an incoming frame rate. The motion artifact reduction system (10) also has a processor (12) operable to determine whether an object (O) having a first location (Om) in a first image frame (IFm) is sufficiently displaced from a location (Om+1) in a second image frame (IFm+1) corresponding to the first location (Om). The processor (12) is also operable to interpolate data from the first image frame (IFm) and the second image frame (IFm+1) to create a third image frame (OFn+1) including the interpolated data. The processor (12) is also operable to insert the third image frame (OFn+1) between the first image frame (IFm) and the second image frame (IFm+1) to form a new series (OFn, OFn+1, and OFn+2) in response to the determination that object (O) has been sufficiently displaced between image frames (IFm, IFm+1).

Abstract: Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1−D)(1+D)3 to the detected EPR4 bits.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal, usually copper or a copper alloy, having a modified surface adapted to provide bondability and solderability and adhesion to polymeric compounds. The modified surface comprises a layer created by converting a percentage of base metal atoms into substitutional metal complexes, usually hydrated chromates. A thin layer of plated copper may be employed for controlling uniformity and consistency of the replacement reaction.

Abstract: The present invention relates to a Class D amplifier and method dynamically modulate the transition zone of a square wave as a function of the input signal. An embodiment of the amplifier a pseudo noise code generator to generate a signal for spreading processing which connects to a triangle oscillator to oscillate the spreading processing signal. A modulator having an audio input port such that the modulator dynamically modulates the oscillated spreading processing signal as a function of the input signal is also included. Dithering the frequency with a Pseudo Noise (PN) code spreads the spectrum of the pulse width modulated (PWM) output; thus, eliminating the need for a demodulating filter. The modulator couples to a power amplifying switching circuit, being operative to generate a power amplified audio drive signal for application to an audio output load port in accordance with the output of the modulator.

Abstract: A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. A plurality of algorithm modules is combined with a framework to form the software program. Each of the plurality of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The software program is then loaded on a hardware platform and executed. During execution, the framework sends a query to the memory interface of each of the plurality of algorithm modules to request memory usage requirements for each instance of each of the plurality of algorithm modules.

Abstract: A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).

Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.