Abstract: An apparatus for the fabrication of a semiconductor device comprising: a mold having top and bottom halves, each with cavities for holding semiconductor chips pre-assembled on an electrically insulating interposer; one of said halves having a plurality of runners and a plurality of gates for feeding encapsulation material into said cavities; said plurality of runners comprising pairs of runners parallel to each other, having gates opposite to each other, thereby forming dual gates; each pair of runners being configured such that encapsulation material will exit from adjacent gates concurrently; and each pair of dual gates being structured such that they fill the cavity between them uniformly with encapsulation material, thereby encapsulating thin semiconductor devices.

Abstract: A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.

Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.

Abstract: This invention is a remotely controllable clock circuit embodied in a single integrated circuit device. The clock circuit includes at least one externally writable clock control register, a reference clock input, a controllable oscillator circuit, a pre-scalar circuit and a comparison circuit. The comparison circuit controlling the frequency of the controllable oscillator circuit to achieve a frequency match between a pre-scaled reference clock signal and a pre-scaled oscillator clock signal. The pre-scale divide factors are stored in respective fields in the clock control register. The clock control register may be memory mapped into a device memory space, accessed via an indirect access register or accessed via a serial scan chain. A trace first-in-first-out buffer has an input for trace data operating under the function clock signal of the operating circuits and an output operating under the oscillator clock signal.

Abstract: The temperature compensated threshold circuit includes: a positive trip point circuit 60 for providing a positive trip point when an input voltage PSM is higher than a positive supply voltage VCC; a negative trip point circuit 62 for providing a negative trip point when the input voltage PSM is below a negative supply voltage AGND; and a bias circuit 64 for providing to the positive and negative trip point circuits 60 and 62 a first current proportional to absolute temperature and a second current proportional to a base emitter voltage.

Abstract: Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a memory cell. The plugs may be formed by implanting regions in high resistivity material above and below a phase change material layer to lower the resistivity in the implanted regions.

Abstract: A system 400 and method 1200 is disclosed for a fast locking (e.g., within 1.5 sync bit times or the first data transition) clock and data recovery (CDR) system used in high speed data communications applications (e.g., ASIC and microprocessor chips). The CDR circuit takes multiple (e.g., 8) phases of the local clock, which are offset (e.g., by 45 degrees), and uses the multiple phases to latch the state of data at multiple times, and uses the latched data to determine which of the multiple phases captured a data transition. The CDR circuit compares the indicated phase to the phase used to capture a previous data transition and uses such information to, produce a stable selection of a clock phase. The selected clock phase is then employed to provide a recovered clock and data signals (CLK_OUT, and DATA_OUT), in association with the incoming serial data stream independent of jitter and free of metastable conditions.

Abstract: A rail-to-rail class AB output stage includes a P-channel pull-up transistor (4) having a source coupled to a first supply rail voltage (V+), a gate coupled to a first input conductor (2) of the output stage, and a drain coupled to an output terminal (6) of the output stage. An N-channel pull-down transistor (5) includes a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor (3) of the output stage, and a drain coupled to the output terminal (6). A P-channel first bias transistor (20) includes a source coupled to the first input conductor (2) and a drain coupled to the second input terminal (3). A first bias circuit coupled between the first and second supply rail voltages produces a first bias voltage (21) on a gate of the first bias transistor (20). A P-channel second bias transistor (10) includes a source coupled to be first input conductor (2).

Abstract: A method for use in a system including an analog-to-digital converter subsystem (ADC) and a digital-to-analog converter subsystem (DAC), wherein the ADC samples an input signal at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input signal. The method is applicable to such systems in which the DAC includes a plurality of elements, such as capacitors or current sources, each connectable in a plurality of different ways in accordance with the digital outputs so as to contribute a portion of an analog output signal corresponding to the digital output, the magnitude of the portion being determined by a way the element is connected. The method is one for shuffling the elements, and includes the following steps. A plurality of coded analog signals are generated based on the input voltage, each such coded analog signal being above or below a predetermined threshold so as to correspond to a way one of the elements is connected.

Abstract: An integrating rod (100) for combining light beams from two or more sources. A first light beam (104) enters the integrating rod 100 through a first entrance face (102) to a first reflecting face (110). The light is reflected by the first reflecting face (110) and travels along the major axis (114) of the integrating rod (100) to an exit face (116). A second light beam (108) from a second light source enters the integrating rod (100) through a second entrance face (106). The second light beam may be reflected by a second reflecting face (112) and travels along the major axis (114) to the exit face (116). The two light beams experience multiple reflections as they travel along the integrating rod and leave the integrating rod (100) through the exit face (116) as a single homogenous light beam.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: A method for providing a multi-stage filter on an input stream of digital data. In the method, the input stream of digital data is operated on with a first polyphase filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a second polyphase filter routine. An optimizing indexing procedure is applied in performing instructions of the routines so as to execute fewer instructions that do not generate intermediate data on which the output stream of data is based.

Abstract: A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

Abstract: Methods are disclosed for manufacturing semiconductor device dies and for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for securing a semiconductor device to a surface. Semiconductor wafers and die are also disclosed having contoured bottom surfaces.

Abstract: The present invention relates to a high speed sample and hold circuit having a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also having a calibration sample and hold subcircuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a timing for one or more of the plurality of sample and hold subcircuits to thereby reduce sampling mismatch between the plurality of sample and hold subcircuits. The present invention also having a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.

Abstract: A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage.

Abstract: A peak hold circuit that can operate to follow changes in peak value even if the changes are abrupt. The peak hold circuit (1) of the present invention has current control circuit (31), auxiliary switch element (25), and auxiliary constant current circuit (26). Current control circuit (31) counts the number of reference clock pulses RCK after output signal Vout becomes higher than analog voltage DI. When the number of clock pulses counted reaches a prescribed number or larger, auxiliary switch element (25) is turned on to operate auxiliary constant current circuit (26) to increase the amount of drop of output signal Vout per unit time. Consequently, even if output signal Vout becomes higher than the peak value of analog voltage DI, it is possible, by increasing the amount of drop of output signal Vout to make output signal Vout lower than analog voltage DI in a shorter amount of time than in the case in the conventional technology.

Abstract: The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier 20 having a first input coupled to a reference voltage node Vref; a second amplifier 22 having an input coupled to an output of the first amplifier 20; a pass transistor 24 having a control node coupled to an output of the second amplifier 22; a feedback circuit 26 and 28 having an input coupled to the pass transistor 24 and an output coupled to a second input of the first amplifier 20; an inverting gain stage 36 coupled to the input of the second amplifier 22; and a high pass filter 42, 44, and 38 coupled between a power supply node and a control node of the inverting gain stage 36. The circuit uses the high pass filter 42, 44, and 38 and inverting gain stage 36 to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node Vo.

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal.

Abstract: A method of patterning a metal layer that cleans the residue from a metal etch process without removing a photoresist etch mask. The method is particularly useful for the fabrication of micromirror devices, or other MEMS devices that use photoresist spacer layers. A photoresist layer is spun on to the mirror metal layer in step 906. The photoresist is patterned and developed in step 908 to form openings to the metal layer. The openings define areas where the mirror metal layer will be removed. The patterned photoresist is inspected in step 910. The mirror metal layer is etched in step 912 using the patterned photoresist layer as an etch mask. After the mirror metal has been etched, the webbing and other residues are removed in a clean up process 914 that uses photoresist developer as a solvent to remove the webbing. After the developer clean up process, the mirrors are inspected in step 916 to verify the proper gaps have been etched between the mirrors and the removal of the mirror etch residue.