Abstract: A collection of program instructions capable of executing on a host processor suitable for reading from a memory location of a target processor and suitable for creating a real-time data channel between said host and target processors.

Abstract: The amplifier output stage circuit includes: a translinear loop 30 having first and second input nodes Vin+ and Vin−; a first transistor Q7 coupled between a first output node of the translinear loop 30 and a first supply node V+; a first output transistor Q9 coupled between an output node 36 of the circuit and the first supply node V+, and having a base coupled to a base of the first transistor Q7; a second transistor Q10 coupled between a second output node of the translinear loop 30 and a second supply node V−; a second output transistor Q12 coupled between the output node 36 of the circuit and the second supply node V−, and having a base coupled to a base of the second transistor Q10.

Abstract: A heuristic based motion estimation system and method for video compression may include: defining the target block 70; defining a simplified signature block 72; searching the reference frame using the simplified signature block 74; searching for the best match in the area centered around the location of the target block in the reference frame using the simplified signature 76; computing the sum of the absolute pixel-by-pixel difference using motion vectors of the target block's neighbors and a zero motion vector 78; selecting a new block with a motion vector with the minimum sum of the absolute pixel-by-pixel difference 80; and searching adjacent neighbors of the new block for minimum absolute difference match 82.

Abstract: A method (40) of determining a best focus for an integrated circuit stepper (10). The method repeats various steps for a plurality of different focus levels. The repeated steps include forming a first element group (C1) on a wafer (30F1), where the first element group comprises one or more elements and each of the one or more elements in the first element group has a shape. The repeated steps further include defining a first reference point (CC1) for the first element group at a position relative to the shape of the one or more elements in the first element group. Similarly, the repeated steps include forming a second element group (C2) on the wafer, where the second group comprises one or more elements and each of the one or more elements in the second element group has a shape, and defining a second reference point (CC2) for the second element group at a position relative to the shape of the one or more elements in the second element group.

Abstract: This invention employs probabilistic templates, or p-templates, which probabilistically encode the rough position and extent of the tracked object's image. The p-templates track objects in the scene, one p-template per object. They can be used to incorporate three-dimensional knowledge about the scene, and to reason about occlusion between the objects tracked by the p-templates. This invention requires video capture and digitization hardware, image processing hardware such as a digital signal processor, and a method for estimating the image size of a person standing at a given location in the image.

Abstract: Low-cost plastic cavity-up land-grid array packages and ball-grid array packages are provided, suitable for wire-bonded chips having micromechanical components. The packages feature a thermal heat spreader and a protective lid. The package structure disclosed is flexible with regard to materials and geometrical detail, and provides solutions to specific functions such as storage space for chemical compounds within the enclosed cavity of the package.

Abstract: Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective architecture registers as specified by the corresponding instructions (from which the results are generated). A forwarding multiplexor receives the results before the results are provided to the register input multiplexors, and selects one of the results for use as an operand for execution of a dependent instruction. As the forwarding multiplexor receives the results at a point before the inputs of the register input multiplexors, the time duration required to forward the results may be minimized, and a greater instruction throughput performance may be attained in a processor.

Abstract: Determining whether a device is defective by analyzing the sound signals generated by the device. Digital samples are generated to represent the sound signals. Digital samples are transformed from the time domain to the frequency domain to generate a frequency spectrum. By comparing the levels of intensity at a corresponding frequency to the threshold levels of intensity, defective devices can be determined.

Abstract: A preamplifier system includes an amplifier stage having at least one feedback network. The feedback network has a feedback resistance that may be adjusted to improve a frequency response of the preamplifier. A feedback control system is operative to set the resistance of the feedback network as a function of a resistance value of an associated read/write head.

Abstract: A system and method are disclosed for restricting process fluid flow within a showerhead assembly which includes a process chamber (12) with a showerhead assembly (20) disposed therein. The showerhead assembly (20) has a blocking assembly (24) disposed within the showerhead assembly (20) for restricting the flow of process fluid within the showerhead assembly (20). Restricting the flow of process fluid within the showerhead effectively restricts the flow of process fluid exiting a center portion (30) of showerhead assembly (20), directed at a substrate wafer (16) disposed within the process chamber (12).

Abstract: A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis.

Abstract: An integrated circuit (10) includes a device such as a transistor. A layout (90) of the device is prepared, which in the case of the transistor includes a ground plane section (52), spaced diffusion sections (56A-56B) and a gate section (57). In order to accurately identify all capacitances associated with the transistor, the gate section is subdivided into three subsections (57A-57C) which are treated as electrically separate, and the two diffusion sections are treated as electrically separate from structure external to the transistor that is electrically coupled to them. Capacitances are then identified between each pair of the electrically separate portions. Some of the identified capacitances may optionally be discarded. Capacitances identified for various portions that are actually in electrical contact are then summed in a specified manner, after which the summed capacitances are used to facilitate simulation of the operation of the integrated circuit.

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: An instrumentation amplifier is provided which can provide high common mode rejection without the use of precision resistors. The instrumentation amplifier can be configured in an 8-pin layout, such as, for example, for an MSOP-8 or SO-8 surface mount package. In addition, an instrumentation amplifier can be provided which can effectively cancel the differential mode signal created by common mode input signals, such as those caused by parasitic capacitance and the like. As a result, the instrumentation amplifier can exhibit excellent AC as well as DC common mode rejection. In accordance with an exemplary embodiment, an instrumentation amplifier can comprise two pairs of current mirrors configured with two buffers to suitably add the differential current-mode signals and subtract the common current mode signals of each buffer to thereby cancel the differential mode signal created by common mode input signals, such as those caused by the parasitic capacitances within the instrumentation amplifier.

Abstract: A method and apparatus for reducing the color separation in sequential color display systems. The disclosed approach adds a white (clear) segment 923 to the color filtering system 92 and applies an algorithm, which separates the luminance channel as much as possible into this white segment. As a result, in the case of a black-and-white image where color separation is most visible, color segments will have a minimal amount of energy in them, thereby reducing the color separation effect. The algorithm controls the process of transferring the energy from the colored segments into the white segment and also allows for a dynamic mode, where on a pixel-by-pixel basis, both color separation reduction is made for the white portions of the image and overall image brightness is improved in the non-white (color) portions of the image.

Abstract: A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Abstract: In hard disk drives (HDD), a magnetic read head moves over a portion of the hard disk when reading data. A preamplifier, having an initial amplification stage of the single ended type, connects to the magnetic read head and amplifies a data signal picked up by the magnetic read head. The preamplifier typically has multiple read heads, or channels. In order to reduce noise coming into the read channels of the preamplifier from the substrate capacitances of the input transistors connected to the read heads, the input transistors are grouped together into multiple banks that are multiplexed, or turn on separately. To further aid noise reduction, the poles of the single ended amplifier are matched, that is, the frequency response of the constant voltage side is matched to the frequency response to the signal side. This effectively reduces both ground noise and Vcc power supply noise as the the noise becomes common mode on the inputs to a differential amplifier that is connected to the single ended amplifier.

Abstract: A data processing system for the compression and decompression of data using Differential Pulse Code Modulation, and optimized for fast execution using a parallel processing DSP such as the Texas Instruments TMS320C8X family. Decompression is speeded up over the methods known in the art by combining the VLC codes and the additional interval bits into one code, which is then used as an index into a Look Up Table that yields the final result in one step instead of the multiple operations required by current implementations.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.