Abstract: A differential line driver with 4X supply voltage swing with a 1:1 transformer, which enhances the loop length for applications such as digital subscriber line includes: a differential circuit having first and second input nodes, first and second output nodes 52 and 54, and a supply voltage node; a transformer 22 having a first coil coupled between the first and second output nodes; and a center tap 50 of the first coil coupled to the supply voltage node. The device also acts as an active impedance termination, which eliminates the series termination resistor in conventional hybrids and thereby saving 6 dB transmit power.
Type:
Grant
Filed:
August 24, 2001
Date of Patent:
March 25, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Kambiz Hayat-Dawoodi, Anil Kumar, Fernando D. Carvajal
Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.
Type:
Grant
Filed:
July 30, 2001
Date of Patent:
March 25, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Ka Y. Leung, James L. Todsen, Binan Wang, Abdullah Yilmaz
Abstract: A switching power supply circuit display an oscillation frequency will not be lowered with a light load. After the first output transistor 11 turns from conduction to cut-off, when the second output transistor 12 conducts, first, by means of the energy accumulated in the inductance element 13, a current will flow from the source terminal toward the drain terminal of the second output transistor 12, and then by means of the discharge of the output capacitor 14, a current will flow from the drain terminal toward the source terminal. Next, in case of a light load, the second output transistor 12, before being cut off by the control circuit 20, is cut off by the frequency control unit 50. By means of the discharge of the output capacitor 14, the lowering of oscillation frequency in case of a light load is prevented.
Abstract: A lead frame for an integrated circuit includes a ground for the integrated circuit to ground the integrated circuit, the lead frame having at least one corner connected to the ground; and a connector between the corner of the lead frame and the ground located on the integrated circuit.
Abstract: A circuit and method are presented for detecting a fault in a magneto-resistive head (18). The circuit includes a bias circuit (50) to produce a bias voltage across the head (18) and a pair of resistors (68,70) in series with the head (18) connected to the bias circuit (50) to carry a current (IVMR) from the bias circuit (50) in common with the head. A circuit (102,102′) is provided to determine a ratio of a voltage across the head (18) with respect to a voltage across the head (18) and the pair of resistors (68,70), and a circuit (104,106,104′,106′) is provided for indicating a fault if the ratio falls outside a predetermined range.
Abstract: Noise-shaped dynamic element matching in analog-to-digital and digital-to-analog converters is increased in such a way that the number of components increases linearly, rather than exponentially, as the number of bits is increased. A processor generates a plurality of input signals for a plurality of digital delta sigma modulators which, in turn, generate a plurality of control signals for selecting a plurality of weighted converter elements. The processor recursively generates the input signals in such a way that the control signals generated by some of the digital delta sigma modulators include error cancellation components to cancel error components in other control signals.
Abstract: A tunnel diode construction 12 for an EEPROM device 10, and method for making it are shown. A tank 13 is provided at a surface of a semiconductor substrate 5 containing a doped diffused tunnel region 46. A layer of insulation 38 is provided over the surface of the substrate with a first thickness 48 to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness 39 elsewhere. A conducting floating gate 19 is provided above the doped diffused tunnel region 46 and at least part of the tank 13, on the layer of insulation 38. The floating gate 19 extends over the oxide 38 beyond the lateral boundaries of the doped diffused tunnel region 46 in every direction to terminate over the second thickness of oxide 39 over the tank 13.
Abstract: A read/write head assembly (20) is provided for use in a mass storage device such as a hard disk. drive. The read/write head assembly (20) is positioned on a suspension arm (18) and includes a read/write head (24) and a head lifter (22). The head lifter (22) positions the read/write head (24) in a first position and a second position.
Abstract: A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one cache upon a direct memory access to the directly addressable memory. The snoop unit generates a write snoop access to both level one caches upon a direct memory access write to or a direct memory access read from the directly addressable memory. The level one cache also invalidates a cache entry upon a snoop hit and also writes back a dirty cache entry to the directly addressable memory. A level two memory is selectively configurable as part level two unified cache and part directly addressable memory.
Type:
Grant
Filed:
June 26, 2000
Date of Patent:
March 18, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Charles L. Fuoco, Sanjive Agarwala, David A. Comisky, Timothy D. Anderson, Christopher L. Mobley
Abstract: A peak detector for detecting a peak signal includes an input circuit for inputting an input signal, a differential comparator for comparing the input signal with the peak signal to generate a difference signal, a diverting circuit to divert current between a first current path and a second current path based on the difference signal, and a comparator to accept current from the first current path and not from the second current path and to form the peak signal resulting from the current.
Abstract: The object of the invention is a system and method for identifying and communicating with a plurality of transponders which are at the same time in the same interrogation field. The system is based on an interrogator which sends interrogation bursts in a periodical manner, and transponders which send the response back with a random delay related to the end-of-burst event. The system is primarily suitable for passive (no additional power supply) transponders, but can also be used for active transponders.
Type:
Grant
Filed:
December 1, 1998
Date of Patent:
March 18, 2003
Assignee:
Texas Instruments Sensors and Controls, Inc.
Abstract: A method of fabricating a transistor using silicon on lattice matched insulator. A first monocrystalline silicon layer is provided and a first layer of dielectric is epitaxially deposited over the first silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A first electrically conductive gate electrode is epitaxially formed over the first layer of dielectric substantially lattice matched with the first layer of dielectric. A second layer of dielectric is epitaxially deposited conformally over the first gate electrode and exposed portions of first layer of dielectric substantially lattice matched with the first silicon layer and substantially monocrystalline. A second monocrystalline silicon layer is epitaxially deposited over the second layer of dielectric and a third layer of dielectric is epitaxially deposited over the second silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline.
Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.
Abstract: The present invention provides technical advantages as a class AB output driver (400) with minimal cross-over distortion. If the differential input to the driver is I+&dgr;I/2 and I−&dgr;I/2, then the current gain is the average of &bgr;n and &bgr;p, more specifically, (&bgr;n−&bgr;p)*I+((&bgr;n+&bgr;p)/2)* &dgr;I. The offset current (&bgr;n−&bgr;p)*I is taken out with a feedback loop.
Abstract: A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, by modifying NOP instructions to minimize bit changes from cycle to cycle in the machine code. Specifically, a NOP is replaced with a proxy NOP, whose syntax is the same as an adjacent instruction but that is treated as a NOP. This modification results in reduced power dissipation.
Abstract: The leakage current correction circuit uses a dummy device Mleak to detect leakage current. The dummy device is a scaled down version of the pass element Mpass. A current router is used to either gain up the dummy leakage current and apply it to the output Vout or simply dump the small un-gained current to ground GND.
Abstract: A multi-channel interleaved power converter includes first and second per-channel conversion circuits, each including a pulse width modulator (PWM), a driver PWM, an output inductor carrying load current, and a current controlled current source (CCCS) coupled to sense the inductor current. The inductors of the different channels are coupled in common to an output node of the power converter. Summing circuitry is operative (i) to subtract the output current of the second channel CCCS from the output current of the first channel CCCS, (ii) to convert the difference current into an offset, and (iii) to apply the offset to a first PWM control signal to generate a second PWM control signal for the second channel. The PWM control signals cause respective currents to be established in the inductors of the different channels according to a predetermined desired current relationship, such as equality.
Type:
Grant
Filed:
June 18, 2002
Date of Patent:
March 18, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
James Edward Wells, Norbert James Hepfinger
Abstract: The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry which comprises an integrated circuit having at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.
Type:
Grant
Filed:
March 18, 1998
Date of Patent:
March 18, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Charvaka Duvvury, Michael D. Chaine, Puvvada Venugopal
Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.
Type:
Grant
Filed:
April 11, 2001
Date of Patent:
March 18, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Roger J. Stierman, Thomas M. Moore, Gregory B. Shinn
Abstract: A predriver receives control information and provides an output signal for implementing control of an associated power switch device. The control information triggers a change in the output signal, such as from a first generally stable level to a second generally stable level. During the change in the output signal, the predriver operates in at least two transitional modes to control the output signal. The different transitional modes, for example, cause the output signal of the predriver to change at different rates. An associated pair of high side and low side predrivers further can be implemented in combination with a set of respective high side and low side power switches so as to form a driver.