Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: A controller for a switching power supply having first and second synchronous rectifiers that minimizes the reverse recovery time and body diode conduction losses of each of the synchronous rectifiers. The controller includes a first controller that predicts the optimal turn-on and turn-off time of the first synchronous rectifier as a function of voltage measurements of the previous switching cycle and the timing of the pulse width modulator signal in the current switching cycle. The controller also includes a second controller that predicts the optimal turn-on and turn-off time of the second synchronous rectifier as a function of voltage measurements of the previous switching cycle and the timing of the pulse width modulator signal in the current switching cycle.

Abstract: A photocell for detecting light includes at least two tiers or structures, one disposed over the other, each tier having a metal-insulator-semiconductor (M-I-S) or a semiconductor-insulator-metal (S-I-M) structure. Each M-I-S structure includes a semiconductor diffusion layer capable of developing a depletion region, a thin insulator layer disposed on the diffusion layer, and a contact layer disposed on the thin insulator layer. Each S-I-M structure includes a contact layer, a thin insulator layer disposed on the contact layer, and a semiconductor diffusion layer disposed on the thin insulator layer, the semiconductor layer capable of developing a depletion region. When light is incident on each depletion region, a current indicative of the light detected in each depletion region flows through the respective contact layer. Also provided is a semiconductor-insulator-metal (S-I-M) structure that detects light. Two- and three-tiered photocells made of M-I-S and/or S-I-M structures are also provided.

Abstract: A method of making a ball grid array package wherein there is provided a partially fabricated package including a semiconductor die, leads and balls secured to predetermined ones of the leads. The leads and balls are concurrently coated with palladium. The die, leads and at least a portion of each of the balls are then encapsulated. Encapsulation includes providing a mold including a plurality of recesses, each recesses for receiving one of the balls. A plurality of cavities is provided in the package, each extending to one of the leads at the location of one of the balls. A plurality of mold members is provided, each extendable into one of the cavities to apply a force against the ball associated with the lead to which the cavity extends. The partially fabricated package is placed into the mold so that the balls extend into the recesses and the mold members extends into the cavities. The molding material is applied to the mold cavity to provide the encapsulation.

Abstract: The invention relates to a DC/DC converter circuit including a voltage conversion circuit and a regulator circuit comprising a reference voltage generator circuit and a comparator which outputs a control signal for activating/deactivating the voltage conversion circuit as a function of the output load of the converter circuit.

Abstract: A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a comparator (66) that compares a signal (104) indicating a value of the power supply to a ramp wave (69). An output of the comparator (66) is a signal containing a time width proportional to the output of the power supply. Additionally, a first comparator (90) compares the output voltage (42) to a first reference voltage (94). When the output voltage (42) exceeds the first reference voltage (94), the first comparator (90) changes state. A second comparator (88) compares the output voltage (42) to a second reference voltage (92). When the second reference voltage (92) exceeds the output voltage (42), the second comparator (88) changes state. The pulses are width modulated to first or second width limits in response to changes of output states of the first and second comparators.

Abstract: A method of processing print data allowing for rendering bands of print data in parallel. A main processor (52) of a single-chip multiprocessor converts an incoming page of print data into paths. The paths are then converted to primitives and the primitives are rasterized using parallel processor (60, 62, 64, 66). The parallel processors (60, 62, 64, 66) work in concert with the main processor (52) such that bands of the final print image are rendered into a frame buffer (58) in parallel, allowing for faster and more efficient processing of print data.

Abstract: A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status for the sector (16) and is independently erasable from the sector (16). A state machine (30) is operable to perform operations on the sectors (16). The state machine (30) is also operable to adjust the status indicator set (20) for a sector (16) prior to performing an operation on the sector (16) to indicate an interruption status and to adjust the status indicator set (20) for the sector (16) after completing the operation to indicate a completed status. Status indicator set (20) preferably includes alternatively employed active indicator sub-sets and erase indicator sub-sets.

Abstract: An isolated integrated differential current comparator for comparatively measuring the current passing through one or two resistors using a thermal difference sensor employing the Seebeck effect in an integrated circuit that is coupled to the resistors. The thermal difference sensor detects the temperature difference between the resistors, which is proportional to the square of the current passing through them. The output of the current comparator is electrically isolated from the inputs. The output is scalable and in circuit topologies requiring full signal isolation. The integrated differential current comparator is applicable to hot swap applications and applications where isolation of a number of signals is needed.

Abstract: A method and apparatus for encapsulating an integrated circuit die and leadframe assembly. A prepackaged sproutless mold compound insert 71 is placed in a rectangular receptacle 91 in a bottom mold chase 81. The receptacle is coupled to a plurality of die cavities 85 by runners 87. Leadframe strip assemblies containing leadframes, integrated circuit dies, and bond wires coupling the leadframes and dies are placed over the bottom mold chase 81 such that the integrated circuit dies are each centered over a bottom mold die cavity 85. A top mold chase 90 is placed over the bottom mold chase 81 and the mold compound package 71. The top mold chase 90 has die cavities 95 corresponding to those in the bottom mold chase 81. The mold compound insert 71 is preferably packaged in a plastic film 75 which has heat sealed edges 77. The mold compound is forced through the package 75 and heat seals 77 during the molding process by the pressure applied by a rectangular plunger 101.

Abstract: A differential circuit to read differential data from a disk by a voltage bias includes a read circuit to read the differential data from the disk by maintaining the voltage bias and a feedback circuit to sense deviations in the voltage and to adjust the voltage in response to the deviations.

Abstract: The test system and method described herein reduces the production test time of semiconductor devices. More specifically, the apparatus method in accordance with the present invention reduces the data transfer time between the test body and the test mainframe. The test system includes a workstation, a handling device, a test body and a test mainframe. A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send a m-bit packet of least significant bits for each n-bit code word, where m is proportional to the noise amplitude inherent in the system in terms of least significant bits. In the alternative, a user at the workstation can send control signals to the test body to send a m-bit packet for each n-bit code word.

Abstract: A statistical process control information system includes a process information system (process IS) and an analysis information system (analysis IS). The analysis IS generates a script file and a command file. The script file includes responses to command-line queries generated by a process data extraction program, and the command file includes commands for invoking the process data extraction program and copying an extracted data file to the analysis IS. The analysis IS issues a command to the process IS to execute an extraction command routine, causing the process IS to copy and execute the command file. The analysis IS performs statistical analysis on the extracted data file and creates graphical SPC chart files, including a hypertext summary, and these are posted in a network-accessible database for users.

Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.

Abstract: A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56) has bits corresponding to each pin for driving the signal on the pin (52) to a desired value. An output enable register (58) controls output buffers (62) coupled between the output register (56) and the pins (52). A plurality of mask registers (60) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register (56), the data output register (58) and the output enable register (60) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register (60). Logic (50) accesses the data registers in view of the state of the associated mask register (60).

Abstract: A method for saturating data in a register (100) is disclosed. The method comprises shifting data contents in the register (100) by a saturation value and setting at least one bit equal to a sign bit (110) on the register (100). The method further comprises storing the shifted contents in a temporary register (160), which (160) has compare bits (180). The method further comprises setting high bits (150) and low bits (140) to a positive value when the compare bits (180) are not equal to the sign bit (110) and the sign bit indicates a positive data word in the register (100). The method further comprises setting the high bits (150) and low bits (140) to a negative value when the compare bits (180) are not equal to the sign bit (110), and the sign bit (110) indicates a negative data word in the register (100). The method further comprises shifting the set data contents in the register (100) by the saturation value and setting at least one bit equal to a least significant bit (102) on the register (100).

Abstract: This invention corrects of white spot noise in an imager. If the brightness value of a pixel is greater than the maximum brightness value of eight surrounding pixels, then the compensated output is this maximum brightness value. If the brightness value of the pixel is less than the maximum brightness value, then no compensation is applied. Alternatively the brightness value of the pixel may be compared with the maximum brightness value plus a threshold value. The invention stores correction values for a few pixels. If a particular pixel has a stored correction value, then this is subtracted from the brightness value of the particular pixel and the maximum brightness correction is applied to this difference. The stored correction value is replaced with the difference between the brightness value of the particular pixel and the maximum brightness value if this difference is greater than the stored correction value.

Abstract: In a pulse width modulation controlled three-phase voltage-source inverter having three legs, each leg including two transistors coupled serially between the terminals of a power source and providing a respective drive output, each leg further including a shunt resistor between one of the two transistors and one of the terminals, in which control pulses are applied to each leg during a sequence of pulse periods, and the inverter has a neutral current, a method for determining the phase current for each phase. The method includes the following steps. First, it is determined which two legs have the longest on time for the lower power transistors. The current through the shunt resistors for the determined legs is determined, to obtain a value representative of the phase current for the legs. Finally, the phase current for the leg not sampled during the sector is derived by subtracting the determined phase currents from the neutral current.

Abstract: A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch (34) to clamp the DC level therein for a given pixel. A switch (38) then samples the reset level onto a sampling capacitor (46), and a switch (42) thereafter samples the video signal onto one plate of a capacitor (50). The lower plates of the capacitors (46) and (50) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier (68). An offset is provided by a programmable DAC (26) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors (46) and (50) can be varied to vary the gain of the amplifier.

Abstract: A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first level interconnection layer in both an array portion (30a) and periphery portion (30p) is disclosed. The interconnect material (42, 48) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal (40) in a nitrogen ambient. Titanium silicide (44) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates (16, 18) and the capacitor dielectric (17) are formed over the interconnect material (42, 48), due to the thermal stability of the material. Alternative processes of forming the interconnect material (42, 48) are disclosed, to improve step coverage.