Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract: A method and system for expanding a pixel bitmap mask. The pixel bitmap mask (102) is expanded by the use of a lookup table (104) to create an m*n bit expanded mask, where m is the depth of a screen and n is the number of pixels described by the original pixel bitmap mask (102). The expanded mask is logically ANDed with a foreground screen (106). The inverse of the expanded mask is logically ANDed with existing data in a screen buffer (108). The results of the two AND operations are logically OR'd to create a new screen buffer that is eventually sent to a printer.

Abstract: An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of fabrication process conditions (117), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap (12) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.

Abstract: An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.

Abstract: The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT−; a second high side transistor 26 coupled to a second differential output node OUT+; a first booster circuit 72 coupled to the control node of the first high side transistor 23; a second booster circuit 70 coupled to the control node of the second high side transistor 26. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: An operational amplifier input stage includes a first differential input transistor and a second differential input transistor receiving a differential input voltage. A first translinear loop is coupled to the first differential input transistor and a second translinear loop is coupled to the second differential input transistor. The first and second translinear loops are operable to supply an instantaneous current to the respective first and second differential input transistors to sufficiently charge capacitances therein during slewing conditions.

Abstract: A block based hybrid compression method where the input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the compression method most appropriate for each class is chosen on a block by block basis. Blocks classified as IMAGE may be compressed using Parallel Differential Pulse Code Modulation. This method allows the decompression algorithm to decode multiple pixels in parallel, thus making real time decompression significantly easier to implement. The methods shown will execute very efficiently on a Texas Instruments TMS302C82 multiprocessing Digital Signal Processor.

Abstract: The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.

Abstract: A method and apparatus for selectively scaling portions of image data based on the intensity levels of historical image data. The selective scaling, or level expansion, provides improved images by increasing or decreasing the intensity of a portion of image pixels. Black level expansion reduces the intensity of dark pixels and is appropriate when a relatively large number of the image pixels have a high intensity level. White level expansion increases the intensity of bright pixels and is appropriate when a relatively large number of image pixels have a low intensity level. Level expansion is implemented by using histogram comparators 402 to compare the intensity of each pixel with a threshold, typically on a frame-by-frame basis. When an adequate number of pixels in each frame meet the threshold criteria, the level expansion is increased. Field accumulator 404 is used to determine whether and by how much the image data is scaled.

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: A low voltage, broadband differential operational amplifier which eliminates the long tail current source from the amplifier, thereby relieving the headroom requirements by a few tenths of a volt. An input common mode feedback circuit is used to overcome the problems arising from the removal of the long tail current source of prior art circuits. This circuit monitors the common mode feedback current and when the value of the current exceeds a specified range around the nominal amplifier bias current, an appropriate correction in the common mode input voltage is made. This novel amplifier will be valuable for use in pipelined analog-to-digital converter applications, as well as many other low voltage and/or portable applications.

Abstract: A charge pump circuit is configured for suitably controlling the charging current in the charge pump capacitors. The charge pump circuit comprises an input current controlling circuit comprising a current limiting device for controlling the inrush current, and thus the charging current in the charge pump capacitors. The input current controlling circuit is configured to regulate the average voltage at the output of the current limiting device to correspond to the average voltage at the output of a pass device configured for regulating the output current. Accordingly, the total input current, and thus the charging current in the charge pump capacitors, can be suitably controlled at all times to significantly reduce the impact of any instantaneous charging currents.

Abstract: Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.

Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.

Abstract: A method of communicating from a transmitter to a receiver over a communication medium. For the transmitter, the method includes the step of formatting data into a data stream to be communicated across the communications medium. This data stream comprises a plurality of headers (PACK HEADER). Moreover, for each of the plurality of headers, the method performs two steps. First, the method modifies information encoded by the header by performing a bitwise logical operation between selected bits of the header (B) with a predetermined bit pattern (A). Second, the method transmits the plurality of headers on to the communications medium. For the receiver, the method includes the step of receiving the plurality of headers from the communications medium. Additionally, for each of the received headers, the receiver recovers the information encoded by the header.

Abstract: The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.