Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Abstract: The circuit includes: a transistor 22; and a switch 32 coupled to a backgate of the transistor 22 for switching between a power supply node and current-path node of the transistor 22 to prevent a voltage on the backgate from dropping below the voltage on the current-path node.

Abstract: The present invention provides an apparatus and method of selecting a unique combination of materials and dimensions for fabrication of a micro-electromechanical switch for improved RF switch performance. An electrode material is selected which exhibits a resistivity resulting in improved insertion loss for a predetermined switching speed, a dielectric material is selected which exhibits a permittivity resulting in improved isolation, and an airgap thickness is selected resulting in a pull-down voltage approximately equal to a supply voltage of the micro-electromechanical switch in which the isolation and predetermined switching speed are also functions of the airgap thickness.

Abstract: A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a sample period (606) has occurred. After the ramp node (502) is charged to the first voltage level, the ramp node is charged to a second voltage level during period (610). By precharging the ramp node (502) during the hold period (614), it reduces any leakage current in the SH switch (514), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector (500).

Abstract: A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage shifting a data value to the right and at least one other multiplexor stage shifting to the right. Left and right shifts may thus be obtained by using a single set of multiplexor stages. As a result, time delays and area consumed may be reduced when the upper/lower end of a desired shift value range does not equal 2Q−1, wherein Q equals an integer.

Abstract: A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can conveniently replace the dividend as required for the instruction. The approach can be used to implement, among others, 2N-bit/N-bit (denoted 2N/N) division using an N-bit ALU, N/N division using N-bit ALU. The division can be implemented for all possible values of N without requiring substantially more complexity in the implementation.

Abstract: An analog-to-digital converter 16 includes first and second analog-to-digital converters 22 and 24 both of which receive an input signal. The first analog-to-digital converter 22 is configured to be centered around a first signal level point while the second analog-to-digital converter 24 is configured to be centered around a second signal level point. A decoder 26 receives inputs from the two analog-to-digital converters 22 and 24 and selects between the first analog-to-digital converter 22 output and the second analog-to-digital converter 24 output.

Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device (14) further comprises a USB interface circuit (30) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit (30) comprises a memory area (44, 106) comprising a write endpoint (1062) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding (166) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.

Abstract: A phase-locked loop (PLL), particularly useful for ADSL frequency locking applications, uses inexpensive external components in combination with versatile logic that can be implemented in a programmable logic device or an application specific integrated circuit. The PLL has the ability to revert to center-frequency operation in the absence of a timing reference and to adapt to a variety of reference frequencies through logic selection.

Abstract: A telecommunications system using DSL modems (36, 38) detects on-hook or off-hook states of a local loop telecommunications line (18). If the local loop (18) is in an off-hook state, the normal data communication rates are used. If the local loop is in an on-hook state, the unused voice band is allocated to either the upstream band and/or downstream band of the DSL modems, in order to increase data communication rates.

Abstract: A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a semiconductor material and defining a channel area (66) in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source (S2) comprising a first doped region (581) of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain (D2). The drain comprises a first well (641) adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion (68). The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well.

Abstract: An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest

Abstract: An improved DMD type spatial light modulator having an array of pixels (18). The pixels (18) are of the “hidden hinge” design, each pixel having a mirror (30) supported over a hinged yoke (32). Addressing electrodes (26, 28) on an underlying metallization layer and addressing electrodes (50, 52) at the yoke level provide electrostatic forces that cause the mirrors to tilt and then to return to their flat state. The pixels (18) are designed to provide increased clearance between the leading edge of the yoke (32) and the underlying metallization layer when the mirrors (30) are tilted. Various features of the improved pixel (18) also improve the contrast ratio of images generated by the DMD.

Abstract: An offset circuit to correct an offset between differential signals includes a read circuit to read the differential signals, a circuit to measure the offset of the differential signals, and a programmable trim circuit to compensate for the offset of said differential signals.

Abstract: The present invention relates to circuits and method for providing regulated output voltages from an unregulated input voltage. A switching power supply and/or a switching regulator is provided with a control circuit that controls an input signal to a first and second switch coupled in series to an input voltage. A first inductor or winding is coupled to a node between the first and second switch that provides a primary output voltage during switching of the first and second switches. A second inductor or winding is magnetically coupled to the first winding. An auxiliary switch is coupled to the second winding and to rectify an auxiliary output voltage provided at another end of the switch. The voltage drop of the auxiliary switch is matched with the voltage drop of second switch, so that the two voltage drops across the switches substantially cancel one another out.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: The present invention provides a system and method for preparing semiconductor integrated circuits (“ICs”), particularly ball grid arrays (“BGAs”), quad flat packs (“QFPs”) and dual in line packages (“DIPs”) for failure analysis (“FA”) using a variety of techniques, including emission microscopy (“EM”) and externally induced voltage alteration (“XIVA”). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific combination of currents to compensate for variations in transconductance due to resistor processing variations.

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.