Abstract: An apparatus for correcting for the finite gain of an amplifier assembly in a pipelined analog to digital converter (ADC) is disclosed in which an input signal to an amplifier module of one stage of the pipelined ADC is sampled and provided to the input of an amplifier of a subsequent stage as a feed-forward error correction signal. The feed-forward correction signal is subtracted in the next stage from the output residue signal of the previous stage input to the second subsequent stage amplifier in order to remove part of the output signal from the first stage that includes the finite gain of the amplifier.

Abstract: A system for varying the transmission of an attenuated phase shift mask (14) is provided that includes an attenuated phase shift mask (14), a transparent support (16) and a modulation system (18). The mask (14) comprises a variable transmission material. The transparent support (16) supports the mask (14). The modulation system (18) is operable to apply a variable force at the mask (14) to control the transmission of the mask (14).

Abstract: An integrated circuit memory device includes a wordline stress mode arrangement and a storage cell initialization arrangement with the array of storage cells. In the wordline stress mode arrangement, a plurality of wordlines are run across the array. Each wordline is connected with the gates of transfer transistors of a different row of the storage cells. A decoder, responsive to a control signal, simultaneously applies a supply voltage to the wordlines. The supply voltage may be provided by a selectable magnitude external source. In the cell initialization arrangement, a plurality of complementary pairs of bitlines are run across the array. Each complementary pair of the bitlines interconnects with the storage cells in a separate column of the array. A precharge circuit is arranged for precharging the bitlines to a precharge voltage.

Abstract: An apparatus and method for transmitting graphical representations is disclosed. The present invention has an image generator (112) that generates an image (114) of a head (106) with facial features, including an eye portion (202) that correlates to an eye (240) in the head (106). The apparatus also has a non-updating tracker (116) that searches for an eye target image of the eye (240) in the head (106). The eye portion (202) correlating to the eye (240) is positioned at the target image located by the non-updating tracker (116). The apparatus also has an updating tracker (118) that searches for an updated eye target image when the non-updating tracker (116) is unable to locate the eye target image. The updating tracker (118) also positions the eye portion (202) at the updated eye target image and updates the updated eye target image with the eye portion (202). The updating tracker further determines the location of the eye portion (202).

Abstract: The present invention provides improved slew rate control over a varied operating temperature range. A switching device (P1, N1) receives from a predrive circuit (56) a control signal that limits a slew rate of the switching device's output and also varies proportionally to the operating temperature. In this manner, the effect of temperature on the slew rate can be reduced.

Abstract: A “multi-stage” method of estimating pitch in a speech encoder (FIG. 2). In a first stage of the method, a set of candidate pitch values is selected, such as by using a cost function that operates on said speech signal (steps 21-23). In a second stage of the method, a best candidate is selected. Specifically, in the second stage, pitch values calculated from previous speech segments are used to calculate an average pitch value (step 25). Then, depending on whether the average pitch value is short or long, one of two different analysis-by-synthesis (ABS) processes is then repeated for each candidate, such that for each iteration, a synthesized signal is derived from that pitch candidate and compared to a reference signal to provide an error value. A time domain ABS process is used if the average pitch is short (step 27), whereas a frequency domain ABS process is used if the average pitch is long (step 28).

Abstract: An electronic circuit for converting an analog differential signal into a corresponding digital signal includes 2n voltage comparators each having a first input terminal, a second input terminal and an output terminal. A first network of 2n resistive elements is provided to which a first analog signal of the differential signal is applied, the first network having a plurality of first network nodes each coupled to the first input terminal of a corresponding one of the comparators and wherein one of the first network nodes is a first middle node coupled to the first analog signal. A second network of 2n resistive elements is provided to which a second analog signal of the differential signal is applied, the second network having a plurality of second network nodes each coupled to the second input terminal of the corresponding one of the comparators and wherein one of the second network nodes is a second middle node coupled to the second analog signal.

Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

Abstract: A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20).

Abstract: A housing for a compact high intensity lamp. The housing has a shell whose inner surface generally conforms to the outer profile of the lamp, except at the lamp face. A small air space exists between the inner surface of the shell and the outer profile of the lamp. The shell receives air at an air intake port, and the air circulates in the air space, and exits from an air exhaust port. The shell and the lamp both rest on an alignment collar, that aligns the lamp to the shell and aligns the lamp to other equipment with which it is to be used.

Abstract: A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.

Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a low vapor pressure solvent (such as water and 1-butanol) is disclosed. By a method according to the present invention, such a precursor sol is applied as a thin film to a semiconductor wafer, and the high vapor pressure solvent is allowed to evaporate while evaporation of the low vapor pressure solvent is limited, preferably by controlling the atmosphere adjacent to the wafer. The reduced sol is then allowed to gel at a concentration determined by the ratio of metal alkoxide to low vapor pressure solvent. One advantage of the present invention is that it provides a stable, spinnable sol for setting film thickness and providing good planarity and gap fill for patterned wafers.

Abstract: A GFSK modulator suitable for use in an RF communication system comprising a modular subsystem and a baseband processor subsystem which is implemented digitally. The baseband processor subsystem comprises a Gaussian filter, phase accumulator and cosine and sine look up tables. The baseband processor functions to convert an input data sequence into I and Q output signals. The I and Q signals are subsequently modulated by a quadrature modulator to yield a GFSK modulated signal which can then be amplified and placed into the channel. The response of the Gaussian filter is pre-calculated for all possible combinations of the input data and the results are quantized and stored in a look up table. The quantized phase results (either magnitude or differences), generated in response to the input data, are accumulated digitally and converted to I and Q signals.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Abstract: In systems requiring the alignment of two clock signals or the alignment of a clock signal to a serial data stream, a current mode interpolator is often used to position the output clock signal. Traditional scan tests using external pins of the device are inappropriate because of their timing penalty and other built in self tests are inappropriate because of a large area or circuit complexity penalty. Therefore, a built in self test has been developed that does not impact the normal performance of the device and requires minimal additional circuitry. In this method, a small digital state machine is utilized to force the digital control logic for the current mode interpolator such that a single bit current comparator is sufficient to detect defects in the digital control logic and the current mode interpolator.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using selective etchants consecutively until the metal layers over the bond pads are removed without damaging the copper metallization. Replacement metal layers are finally deposited over the bond pads. Specifically, the bondable metal, such as gold, is selectively removed by a cyclic dithio-oxamine compound, dissolved in tetra-hydro-furane or acetone. The barrier metals, such as nickel and palladium, are removed by a mixture of inorganic and organic oxidizing acids.

Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

Abstract: A silicon-on-insulator (SOI) SRAM memory cell having a plurality of MOS transistors wherein one or more of the conductive bodies of the transistors are connected by semiconductor material which extends beneath a partial (shallow) trench.

Abstract: A mass data storage device (10) and methods for making and using it are disclosed. The mass data storage device (10) has a read/write head (18) carried in proximity to one end of a selectively positionable arm (42), and an actuation device (20) in proximity to another end of the arm for moving the arm in response to an input signal (31). The mass data storage device (10) has a sensor, such as an accelerometer (38), or the like, carried on the arm (42) for generating a motion signal for use in position control of the arm (42). The sensor (38) is located on the arm (42) at a location at which the motion signal (39) and the actuator input signal (31) have a minimum phase difference. The signal (39) from the sensor (38) may be fed back to control the actuation device (20), and may include a filter (60) that shapes the motion signal to equalize any resonances in the arm or rejects torque effects of the arm (42).