Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.

Abstract: A “multi-stage” method of estimating pitch in a speech encoder (FIG. 2). In a first stage of the method, a set of candidate pitch values is selected, such as by using a cost function that operates on said speech signal (steps 21-23). In a second stage of the method, a best candidate is selected. Specifically, in the second stage, pitch values calculated from previous speech segments are used to calculate an average pitch value (step 25). Then, depending on whether the average pitch value is short or long, one of two different analysis-by-synthesis (ABS) processes is then repeated for each candidate, such that for each iteration, a synthesized signal is derived from that pitch candidate and compared to a reference signal to provide an error value. A time domain ABS process is used if the average pitch is short (step 27), whereas a frequency domain ABS process is used if the average pitch is long (step 28).

Abstract: In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model.

Abstract: The search network in a speech recognition system is reduced by parsing the incoming speech expanding all active paths (101), comparing to speech models and scoring the paths and storing recognition level values at the slots (103) and accumulating the scores and discarding previous slots when a word end is detected creating a word end slot (109).

Abstract: A virtual input queue 80 count frames of data arriving an input port zo in an Ethernet switch 10 using shared memory 50. The shared memory 50 is allocated among 1-N input ports based on either a static or dynamic memory scheme. The static scheme allocates the shared memory 50 evenly among the input ports 20 or based on the input port transmission rate. In the dynamic memory scheme, the range of a virtual input queue's occupancy is divided into an underload zone, a normal load zone and an overload zone. When the virtual input queue is in the underload zone, the input port is kept on and reserved a memory capacity equal to a low threshold. When a virtual input queue is in the normal load zone, the virtual on queue 80 is reserved an additional amount of memory and the link is kept on or is turned on whenever possible. The memory capacity not used or reserved by any input port operating in at least the underload zone and normal load zone is shared by the input ports operating in the overload zone.

Abstract: A charge pump circuit. The circuit includes an input node for receiving a clock signal having cycles. The charge pump circuit includes a pump circuit coupled to the input node, including a first capacitor and having an output node coupled to a second capacitor, the pump circuit operating to provide a predetermined charge the second capacitor in response to a cycle of the clock signal. The predetermined charge corresponds to the amount of charge accumulated on the first capacitor during the cycle of the clock signal.

Abstract: An integrated circuit chip comprising an integrated circuit made in a semiconductor substrate, an information write-register circuit having a plurality of gate-controlled components, such as MOS transistors or capacitors, said write-register being integrated into said circuit yet individually addressable; said components having a gate insulator geometry locally susceptible to electrical conductivity upon applying overstress voltage pulses between said gates and said substrate, whereby information can be permanently encoded into said write-register; and a plurality of level shifter circuits to supply said pulses selectively to said component gates according to stored data and controlled by enable commands, said level shifters being integrated into said circuit.

Abstract: A system (100) for calibrating data converters (101) includes a data converter (101) that receives an input signal and generates one or more pre-digital error correction codes from the input signal. A calibrator (150) receives the pre-digital error correction codes, formulating one or more transition voltage expressions using the pre-digital error correction codes, and compares the transition voltage expressions to one or more measured transition voltage values to generate one or more calibrated values. More specifically, the data converter (101) may be a pipelined analog-to-digital converter (101).

Abstract: A system and method of integrating switching amplifiers into systems with low amplitude front-end tuners to eliminate shielding and EMI filtering associated with signals, power and ground. An adaptive frequency programmable pulse frame rate switching amplifier scheme using either look-up tables or appropriate algorithms, ensures by design, the elimination of critical interference frequency generation.

Abstract: A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including patterning and etching a portion of at least one of said isolation regions to expose a first area of said substrate, depositing a mask layer over said integrated circuit including said first area, patterning an a itching said mask layer to expose a second area of said substrate within said first area, converting a portion of said substrate to a selectively etchable material, wherein said selectively etchable material lies in an area subjacent to said second area and extends only partially to the bottom surface of said substrate, selectively etching said selectively etchable material to form a void, removing said mask layer to expose said isolation region, depositing a dielectric layer over said void wherein said dielectric layer extends at least to the height of said isolation region and covers the top surface of said wafer, polishing the surface of said dielectric la

Abstract: In a system (10) for adding speech recognition capabilities to Java, there is provided a speech recognition server (18) coupled to a Java application (24) through an application program interface (20). The Java application (24) dynamically specifies a grammar (56) to the application program interface (20), which communicates the grammar (56) to the speech recognition server (18). The speech recognition server (18) receives the grammar (56) and a speech input (66). Upon receiving the speech input (66), the speech recognition server (18) performs speech recognition and generates a result (58) based on the grammar (56). The application program interface (20) communicates the result (58) to the Java application (24), which performs an action based on the result (58) received.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state 2300 to transfer state 2310 along arc 2301. The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size.

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: A lateral NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a stopping region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate. The transistor further has in its p-well a region of higher resistivity than the remainder of the well. This region extends laterally from the vicinity of one of the recessed region to the vicinity of the other, and vertically from a depth just below the depletion regions of source and drain to the top of the channel stop region. According to the invention, this region of higher p-type resistivity is created by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants adjusting the threshold voltage and creating the p-well and channel stop.

Abstract: A single voltage controlled oscillator (VCO) running at a closed loop controlled fundamental frequency whereby the harmonic products generated by the VCO are used for both transmission and reception. The use of a single VCO and associated supporting circuitry for both transmit and receive portions of the circuit serves to reduce the cost of the transceiver. The radio transceiver comprises a single synthesized oscillator having high harmonic content. The frequency conversions in the receiver make use of the harmonic frequency components of the same oscillator used in performing modulation during transmission.

Abstract: A method of fabricating solder columns. The method includes the step of providing a substrate having predesignated locations thereon for fabrication of solder columns. An extrusion mold is provided which has apertures extending therethrough and a pair of opposing surfaces. The predesignated locations are aligned with the apertures along one of the surfaces and a solder tape is provided over the other of the opposing surfaces and over the apertures. The portion of the solder tape over the apertures is extruded through the apertures to the one of the surfaces. The portion of the solder tape is heated to at least its flow temperature by heating the substrate and optionally also heating the extrusion mold. The step of extruding comprises the steps of providing a plunger having a plurality of fingers, each finger aligned with an aperture and driving the fingers through the solder tape to drive the solder tape over the apertures to the one of the surfaces.

Abstract: A method for adjusting the output response of a complementary bipolar operational amplifier includes: providing a first bipolar transistor 14; providing a second bipolar transistor 16 coupled to the first bipolar transistor 14; providing a first current source 26 coupled to a base of the first bipolar transistor 14; providing a second current source 28 coupled to a base of the second bipolar transistor 16; providing a third bipolar transistor 10 coupled to the base of the first bipolar transistor 14; providing a fourth bipolar transistor 12 coupled to the base of the second bipolar transistor 16; providing a first resistor 20 coupled between a base of the third transistor 10 and a common node; providing a second resistor 18 coupled between a base of the fourth transistor 12 and the common node; providing a capacitor 30 coupled to the common node; providing a first input stage current source 24 coupled to the first resistor 20; providing a second input stage current source 22 coupled to the fourth resistor 18;

Abstract: A display system (902) and method for increasing the brightness of an image through the use of a color wheel (504) having white light generating segment. The display system comprises a RGBW processing function (906), a hue correction function (906), and a gain correction function (904). The RGBW processing function (906) includes circuitry to generate an intensity word for use during the white light generating segment. The hue correction function (906) includes circuitry to adjust the relative intensities of the primary color components to compensate for the addition of the white segment data. The gain correction function (904) includes circuitry to adjust the intensity of pixel data based on the white content of the pixel and the intensity of the pixel. After the pixel data is processed, it is formatted by data formatting logic (912) and displayed using a spatial light modulator (914).

Abstract: A thin film resonator and method includes a first electrode (110) and a second electrode (112) substantially parallel to the first electrode (110). An intermediate layer (120) is disposed between and coupled to the first and second electrode (110, 112). The intermediate layer (120) includes a first piezoelectric layer (122), a second piezoelectric layer (124), and a spacer layer (130) disposed between the first and second piezoelectric layers (122, 124). The spacer layer (130) has an acoustic impedance substantially the same as the first and second piezoelectric layers (122, 124) and is formed of a disparate material.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor(Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.